Skip to content

Commit 2d8c62f

Browse files
munailwaqarmunailwaqar
committed
icount with action 1
1 parent f96ca65 commit 2d8c62f

File tree

4 files changed

+64
-40
lines changed

4 files changed

+64
-40
lines changed

‎core/csr_regfile.sv

Lines changed: 42 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,9 @@ module csr_regfile
171171
// RVFI
172172
output rvfi_probes_csr_t rvfi_csr_o,
173173
//jvt output
174-
output jvt_t jvt_o
174+
output jvt_t jvt_o,
175175
// action 0 request from trigger module
176-
//output breakpoint_from_tigger_module_o
176+
output logic breakpoint_from_tigger_module_o
177177
);
178178

179179
localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg);
@@ -286,16 +286,16 @@ module csr_regfile
286286
logic [N_Triggers-1:0] tselect_q, tselect_d;
287287
logic [3:0] trigger_type_q[N_Triggers], trigger_type_d[N_Triggers];
288288
logic [CVA6Cfg.XLEN-1:0] scontext_d, scontext_q;
289-
//logic trigger_breakpoint_fire;
290-
//logic breakpoint_from_tigger_module,
291-
//logic priv_match;
289+
logic priv_match;
292290
// icount trigger
293291
icount32_tdata1_t icount32_tdata1_q[N_Triggers], icount32_tdata1_d[N_Triggers];
294292
textra32_tdata3_t textra32_tdata3_q[N_Triggers], textra32_tdata3_d[N_Triggers];
295293
textra64_tdata3_t textra64_tdata3_q[N_Triggers], textra64_tdata3_d[N_Triggers];
296294
logic [CVA6Cfg.XLEN-1:0] tdata2_q[N_Triggers], tdata2_d[N_Triggers];
295+
logic breakpoint_from_tigger_module;
296+
logic in_trap_handler;
297+
logic prev_csr_write;
297298
//icount64_tdata1_t icount64_tdata1;
298-
//logic [13:0] icount_q[N_Triggers], icount_d[N_Triggers]; // because tdata1.count is 14 bits
299299

300300

301301
localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
@@ -1148,7 +1148,6 @@ module csr_regfile
11481148
if (CVA6Cfg.SDTRIG) begin
11491149
if (csr_wdata[31:28] == 4'd3 && CVA6Cfg.XLEN == 32) begin
11501150
trigger_type_d[tselect_q] = csr_wdata[31:28];
1151-
//icount_d[tselect_q] = csr_wdata[23:10];
11521151
icount32_tdata1_d[tselect_q].t_type = (csr_wdata[31:28] == 4'd3 || csr_wdata[31:28] == 4'd4 || csr_wdata[31:28] == 4'd5 || csr_wdata[31:28] == 4'd6 || csr_wdata[31:28] == 4'd15) ? csr_wdata[31:28] : trigger_type_q[tselect_q];
11531152
icount32_tdata1_d[tselect_q].dmode = csr_wdata[27];
11541153
icount32_tdata1_d[tselect_q].vs = 0;
@@ -1160,7 +1159,7 @@ module csr_regfile
11601159
icount32_tdata1_d[tselect_q].s = csr_wdata[7];
11611160
icount32_tdata1_d[tselect_q].u = csr_wdata[6];
11621161
icount32_tdata1_d[tselect_q].action = csr_wdata[5:0];
1163-
//flush_o = 1'b1;
1162+
flush_o = 1'b1;
11641163
end
11651164
end else begin
11661165
update_access_exception = 1'b1;
@@ -2286,27 +2285,35 @@ module csr_regfile
22862285
end
22872286
end
22882287

2289-
// if (CVA6Cfg.SDTRIG) begin
2290-
// if (trigger_type_d[tselect_q] == 4'd3) begin
2291-
// // case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in
2292-
// // riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;
2293-
// // riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;
2294-
// // riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;
2295-
// // endcase
2296-
// // if (commit_ack_i) begin
2297-
// // icount_d--;
2298-
// // end
2299-
// // if ((icache_d == 0) && priv_match) begin
2300-
// //icount32_tdata1_q[tselect_q].pending = 1'b1;
2301-
// //icount32_tdata1_q[tselect_q].hit = 1'b1;
2302-
// // case (icount32_tdata1_d[tselect_q].action)
2303-
// //breakpoint_from_tigger_module_o = 1'b1;
2304-
// //6'd1 : debug_from_trigger_module = 1'b1 //into debug mode;
2305-
// // default: ;
2306-
// // endcase
2307-
// // end
2308-
// end
2309-
// end
2288+
// Triggers Match Logic
2289+
if (CVA6Cfg.SDTRIG) begin
2290+
if (trigger_type_d[tselect_q] == 4'd3) begin // icount match logic
2291+
case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in
2292+
riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;
2293+
riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;
2294+
riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;
2295+
default: priv_match = 1'b0;
2296+
endcase
2297+
if (ex_i.valid) begin
2298+
in_trap_handler = 1'b1;
2299+
icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;
2300+
end
2301+
if (commit_ack_i && mret) in_trap_handler = 1'b0;
2302+
if (|commit_ack_i && !in_trap_handler && icount32_tdata1_q[tselect_q].count != 0) begin
2303+
icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;
2304+
end
2305+
if ((icount32_tdata1_d[tselect_q].count == 0) && priv_match) begin
2306+
icount32_tdata1_d[tselect_q].pending = 1'b1;
2307+
//icount32_tdata1_d[tselect_q].hit = 1'b1;
2308+
case (icount32_tdata1_d[tselect_q].action)
2309+
6'd0 : breakpoint_from_tigger_module = 1'b1;
2310+
6'd1 : breakpoint_from_tigger_module = 1'b1; //into debug mode;
2311+
default: ;
2312+
endcase
2313+
end
2314+
end
2315+
end
2316+
23102317
end
23112318

23122319
// ---------------------------
@@ -2740,17 +2747,17 @@ module csr_regfile
27402747
if (CVA6Cfg.SDTRIG) begin
27412748
scontext_q <= '0;
27422749
tselect_q <= '0;
2750+
prev_csr_write <= 1'b0;
27432751
for (int i = 0; i < N_Triggers; ++i) begin
27442752
trigger_type_q[i] <= '0;
2745-
//icount_q[i] <= 0;
27462753
icount32_tdata1_q[i] <= '0;
27472754
icount32_tdata1_q[i].count <= 1;
27482755
textra32_tdata3_q[i] <= '0;
27492756
textra64_tdata3_q[i] <= '0;
27502757
tdata2_q[i] <= '0;
27512758
end
2752-
//trigger_breakpoint_fire <= 0;
2753-
// priv_match <= 0;
2759+
priv_match <= 0;
2760+
in_trap_handler <= 0;
27542761
end
27552762
// timer and counters
27562763
cycle_q <= 64'b0;
@@ -2837,13 +2844,13 @@ module csr_regfile
28372844
end
28382845
if (CVA6Cfg.SDTRIG) begin
28392846
trigger_type_q <= trigger_type_d;
2840-
//icount_q <= icount_d;
28412847
tselect_q <= tselect_d;
28422848
tdata2_q <= tdata2_d;
28432849
icount32_tdata1_q <= icount32_tdata1_d;
28442850
textra32_tdata3_q <= textra32_tdata3_d;
28452851
textra64_tdata3_q <= textra64_tdata3_d;
28462852
scontext_q <= scontext_d;
2853+
prev_csr_write <= breakpoint_from_tigger_module;
28472854
end
28482855
// timer and counters
28492856
cycle_q <= cycle_d;
@@ -2858,6 +2865,8 @@ module csr_regfile
28582865
end
28592866
end
28602867

2868+
assign breakpoint_from_tigger_module_o = breakpoint_from_tigger_module & ~prev_csr_write;
2869+
28612870
// write logic pmp
28622871
always_comb begin : write
28632872
for (int i = 0; i < 64; i++) begin

‎core/cva6.sv

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -589,6 +589,8 @@ module cva6
589589
logic [31:0] mcountinhibit_csr_perf;
590590
//jvt
591591
jvt_t jvt;
592+
// trigger module
593+
logic breakpoint_from_tigger_module;
592594
// ----------------------------
593595
// Performance Counters <-> *
594596
// ----------------------------
@@ -751,6 +753,7 @@ module cva6
751753
.compressed_valid_o(x_compressed_valid),
752754
.compressed_req_o (x_compressed_req),
753755
.jvt_i (jvt),
756+
.breakpoint_from_tigger_module_i (breakpoint_from_tigger_module),
754757
// DCACHE interfaces
755758
.dcache_req_ports_i(dcache_req_ports_cache_id),
756759
.dcache_req_ports_o(dcache_req_ports_id_cache)
@@ -1207,6 +1210,7 @@ module cva6
12071210
.pmpaddr_o (pmpaddr),
12081211
.mcountinhibit_o (mcountinhibit_csr_perf),
12091212
.jvt_o (jvt),
1213+
.breakpoint_from_tigger_module_o (breakpoint_from_tigger_module),
12101214
//RVFI
12111215
.rvfi_csr_o (rvfi_csr)
12121216
);

‎core/decoder.sv

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,8 @@ module decoder
8989
// Instruction - ISSUE_STAGE
9090
output logic [31:0] orig_instr_o,
9191
// Is a control flow instruction - ISSUE_STAGE
92-
output logic is_control_flow_instr_o
92+
output logic is_control_flow_instr_o,
93+
input breakpoint_from_tigger_module_i
9394
);
9495
logic illegal_instr;
9596
logic illegal_instr_bm;
@@ -1808,9 +1809,6 @@ module decoder
18081809
// set gva bit
18091810
if (CVA6Cfg.RVH) instruction_o.ex.gva = v_i;
18101811
else instruction_o.ex.gva = 1'b0;
1811-
//end else if (CVA6Cfg.SDTRIG && breakpoint_from_tigger_module) begin
1812-
//instruction_o.ex.valid = 1'b1;
1813-
//instruction_o.ex.cause = riscv::BREAKPOINT;
18141812
end
18151813
// -----------------
18161814
// Interrupt Control
@@ -1903,8 +1901,14 @@ module decoder
19031901
end
19041902
end
19051903

1904+
// breakpoint on trigger match (TM)
1905+
// if (CVA6Cfg.SDTRIG && breakpoint_from_tigger_module_i) begin
1906+
// instruction_o.ex.valid = 1'b1;
1907+
// instruction_o.ex.cause = riscv::BREAKPOINT;
1908+
// end
1909+
19061910
// a debug request has precendece over everything else
1907-
if (CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i) begin
1911+
if ((CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i) || (CVA6Cfg.SDTRIG && CVA6Cfg.DebugEn && !debug_mode_i && breakpoint_from_tigger_module_i)) begin
19081912
instruction_o.ex.valid = 1'b1;
19091913
instruction_o.ex.cause = riscv::DEBUG_REQUEST;
19101914
end

‎core/id_stage.sv

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,8 @@ module id_stage #(
9191
input x_compressed_resp_t compressed_resp_i,
9292
output logic compressed_valid_o,
9393
output x_compressed_req_t compressed_req_o,
94+
// breakpoint request from trigger module
95+
input breakpoint_from_tigger_module_i,
9496
// Data cache request ouput - CACHE
9597
input dcache_req_o_t dcache_req_ports_i,
9698
// Data cache request input - CACHE
@@ -285,7 +287,7 @@ module id_stage #(
285287
always_comb begin
286288
// No CVXIF, No ZCMP, No ZCMT => Connect directly compressed decoder to decoder
287289
is_illegal_deco = is_illegal_rvc;
288-
instruction_deco = instruction_rvc;
290+
instruction_deco = instruction_rvc; //breakpoint_from_tigger_module_i ? 32'h00100073 :
289291
is_compressed_deco = is_compressed_rvc;
290292
if (CVA6Cfg.CvxifEn) begin
291293
is_illegal_deco[0] = is_illegal_cvxif_o;
@@ -339,7 +341,8 @@ module id_stage #(
339341
.hu_i,
340342
.instruction_o (decoded_instruction[i]),
341343
.orig_instr_o (orig_instr[i]),
342-
.is_control_flow_instr_o (is_control_flow_instr[i])
344+
.is_control_flow_instr_o (is_control_flow_instr[i]),
345+
.breakpoint_from_tigger_module_i (breakpoint_from_tigger_module_i)
343346
);
344347
end
345348

@@ -439,6 +442,10 @@ module id_stage #(
439442
is_control_flow_instr[0]
440443
};
441444
end
445+
446+
// if (flush_i && !(breakpoint_from_tigger_module_i && !issue_n[0].valid)) begin
447+
// issue_n[0].valid = 1'b0;
448+
// end
442449

443450
// invalidate the pipeline register on a flush
444451
if (flush_i) issue_n[0].valid = 1'b0;

0 commit comments

Comments
 (0)