Board layers: make RAM separate load region for AC6

VladimirUmek · VladimirUmek · commit cff6fc539efa · 2026-03-02T13:23:46.000+01:00
diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
+}
+
+LR_RAM0 __RAM0_BASE {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)

Original file line number	Diff line number	Diff line change
`@@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {`
`48`	`48`	`ER_ROM1 __ROM1_BASE __ROM1_SIZE {`
`49`	`49`	`*(+RO +XO)`
`50`	`50`	`}`
	`51`	`+}`
	`52`	`+`
	`53`	`+LR_RAM0 __RAM0_BASE {`
`51`	`54`
`52`	`55`	`RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {`
`53`	`56`	`*.o(.bss.noinit)`