In CMSIS workflows, which layer is responsible for handling I/D cache coherence?

[jamison-chiu]

Hi,

I couldn't find any information about cache coherence in CMSIS workflows.
https://arm-software.github.io/CMSIS_6/main/General/index.html
For Arm Cortex M55/M85 with I/D cache, does the CMSIS Driver implementation need to handle I/D cache coherence, or do users need to handle it in their applications?

[JonatanAntoni]

Hi @jamison-chiu,

this is a very hot topic. We do not have a strict rule on this as part of CMSIS. Its up to the individual driver implementation and might depend on caching requirements. So far, we didn't consider a one-size-solution to fit all situations.

Cheers,
Jonatan