Description
Description of defect
STM32G0B0 has UARTS which have a FIFO which can be turned on or off. They cannot seem to be turned on when initializing the UART (which happens a lot in mbed: when the BufferedSerial is created, when the format is changed or when the baudrate is changed). There are HAL functions to enable the FIFO but the initialize wipes this setting.
The inability to enable FIFO on initialization is two-fold.
First of all, the general STM serial_api.c
does't seem to allow this. init_uart
contains this code:
#if defined(UART_FIFOMODE_DISABLE) // G0/H7/L4/L5/WB
huart->FifoMode = UART_FIFOMODE_DISABLE;
#endif
UART_FIFOMODE_DISABLE is defined in stm32g0xx_hal_uart_ex.h
:
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
So I'm not sure how to convince the init_uart
in serial_api.c
to set FifoMode to enable this.
Second, setting the FifoMode does not seems to be implemented in UART_SetConfig
in stm32g0xx_hal_uart
(maybe something to raise in STM32CubeG0) . The FIFOMode is part of the CR1 register, so I would expect to see it in this part of the code:
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
I would suggest UART_InitTypeDef
should be extended to contain the FIFOMode as well and change UART_SetConfig
to consider this setting. I also think that using the UART_FIFOMODE_DISABLE
define is the wrong define to determine whether or not the FIFO should be enabled and should be changed by a define generated in mbed_config.h.
I'm obviously willing to make these changes but I'd like your thoughts on the issue first before I fix this.
Target(s) affected by this defect ?
STM32G0B0
Toolchain(s) (name and version) displaying this defect ?
cmake_gcc_arm
What version of Mbed-os are you using (tag or sha) ?
mbed-os-6.15.1
What version(s) of tools are you using. List all that apply (E.g. mbed-cli)
Not applicable
How is this defect reproduced ?
Create a new BufferedSerial and check if the FIFOEN bit is enabled in the UART CR1 register