Merge branch 'nanovdb-vbm-select-decode': rework resolvers to the register decode

Resolve the semantic conflict between the consolidated thread-local decode
(decodeInverseMap into registers; shared-memory decodeInverseMaps removed) and
the stencil resolvers, which consumed the materialized per-block maps:

- Every resolver now takes the calling thread's decoded (leafIndex, voxelOffset)
  by value; the plain forms (forEachBoxStencil, computeCrossStencil) become
  end-to-end thread-local - no shared memory or barrier anywhere in the
  decode+resolve pipeline, safe from divergent threads.
- The cached forms take the block's firstLeafID and jumpMap and derive the
  spanned-leaf count as 1 + the jumpMap popcount (cachedLeafSpan is now a
  thread-local popcount; the shared counter, atomicMax leader election, and two
  of the three prologue barriers are gone). Shared memory drops to the staged
  table alone: 4228 -> 3456 B for the cached box at width 128, 1668 -> 896 B
  for the cached cross.
- The one-thread-per-slot blockDim asserts are dropped: resolvers operate on
  whatever slot the caller passes.

All six resolvers verified byte-exact within their stencil shape (box vs box,
cross vs cross, all 27 taps compared) at widths 128/512 on 16% and 60% leaf
occupancy; VoxelBlockManager unit tests pass.

Signed-off-by: Jonathan Swartz <jonathan@jswartz.info>

Author: swahtz