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Merge pull request #51 from AlexandreSinger/feature-parse-arch
[Parse] Added Metadata Parsing
2 parents 361317f + e721e43 commit 291ac36

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5 files changed

+186
-12
lines changed

5 files changed

+186
-12
lines changed

fpga_arch_parser/src/arch.rs

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,11 @@ pub struct Model {
33

44
}
55

6+
pub struct Metadata {
7+
pub name: String,
8+
pub value: String,
9+
}
10+
611
pub enum PinEquivalence {
712
None,
813
Full,
@@ -137,23 +142,27 @@ pub struct Tile {
137142
pub struct FillGridLocation {
138143
pub pb_type: String,
139144
pub priority: i32,
145+
pub metadata: Option<Vec<Metadata>>,
140146
}
141147

142148
pub struct PerimeterGridLocation {
143149
pub pb_type: String,
144150
pub priority: i32,
151+
pub metadata: Option<Vec<Metadata>>,
145152
}
146153

147154
pub struct CornersGridLocation {
148155
pub pb_type: String,
149156
pub priority: i32,
157+
pub metadata: Option<Vec<Metadata>>,
150158
}
151159

152160
pub struct SingleGridLocation {
153161
pub pb_type: String,
154162
pub priority: i32,
155163
pub x_expr: String,
156164
pub y_expr: String,
165+
pub metadata: Option<Vec<Metadata>>,
157166
}
158167

159168
pub struct ColGridLocation {
@@ -163,6 +172,7 @@ pub struct ColGridLocation {
163172
pub repeat_x_expr: Option<String>,
164173
pub start_y_expr: String,
165174
pub incr_y_expr: String,
175+
pub metadata: Option<Vec<Metadata>>,
166176
}
167177

168178
pub struct RowGridLocation {
@@ -172,6 +182,7 @@ pub struct RowGridLocation {
172182
pub incr_x_expr: String,
173183
pub start_y_expr: String,
174184
pub repeat_y_expr: Option<String>,
185+
pub metadata: Option<Vec<Metadata>>,
175186
}
176187

177188
pub struct RegionGridLocation {
@@ -185,6 +196,7 @@ pub struct RegionGridLocation {
185196
pub end_y_expr: String,
186197
pub repeat_y_expr: Option<String>,
187198
pub incr_y_expr: String,
199+
pub metadata: Option<Vec<Metadata>>,
188200
}
189201

190202
pub enum GridLocation {
@@ -373,20 +385,23 @@ pub struct CompleteInterconnect {
373385
// may be a single pack pattern; however, an interconnect may have many
374386
// pack patterns.
375387
pub pack_patterns: Vec<PackPattern>,
388+
pub metadata: Option<Vec<Metadata>>,
376389
}
377390

378391
pub struct DirectInterconnect {
379392
pub name: String,
380393
pub input: String,
381394
pub output: String,
382395
pub pack_patterns: Vec<PackPattern>,
396+
pub metadata: Option<Vec<Metadata>>,
383397
}
384398

385399
pub struct MuxInterconnect {
386400
pub name: String,
387401
pub input: String,
388402
pub output: String,
389403
pub pack_patterns: Vec<PackPattern>,
404+
pub metadata: Option<Vec<Metadata>>,
390405
}
391406

392407
pub enum Interconnect {
@@ -399,6 +414,7 @@ pub struct PBMode {
399414
pub name: String,
400415
pub pb_types: Vec<PBType>,
401416
pub interconnects: Vec<Interconnect>,
417+
pub metadata: Option<Vec<Metadata>>,
402418
}
403419

404420
pub enum PBTypeClass {
@@ -417,6 +433,7 @@ pub struct PBType {
417433
pub modes: Vec<PBMode>,
418434
pub pb_types: Vec<PBType>,
419435
pub interconnects: Vec<Interconnect>,
436+
pub metadata: Option<Vec<Metadata>>,
420437
}
421438

422439
pub struct FPGAArch {

fpga_arch_parser/src/lib.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ use xml::attribute::OwnedAttribute;
99

1010
mod arch;
1111
mod parse_error;
12+
mod parse_metadata;
1213
mod parse_port;
1314
mod parse_tiles;
1415
mod parse_layouts;

fpga_arch_parser/src/parse_complex_block_list.rs

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ use crate::parse_error::*;
1010
use crate::arch::*;
1111

1212
use crate::parse_port;
13+
use crate::parse_metadata::parse_metadata;
1314

1415
fn parse_pack_pattern(name: &OwnedName,
1516
attributes: &[OwnedAttribute],
@@ -130,6 +131,7 @@ fn parse_interconnect(name: &OwnedName,
130131
};
131132

132133
let mut pack_patterns: Vec<PackPattern> = Vec::new();
134+
let mut metadata: Option<Vec<Metadata>> = None;
133135
loop {
134136
match parser.next() {
135137
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
@@ -148,9 +150,10 @@ fn parse_interconnect(name: &OwnedName,
148150
let _ = parser.skip();
149151
},
150152
"metadata" => {
151-
// TODO: Implement.
152-
// FIXME: Check that this is documented in VTR.
153-
let _ = parser.skip();
153+
metadata = match metadata {
154+
None => Some(parse_metadata(&name, &attributes, parser)?),
155+
Some(_) => return Err(FPGAArchParseError::DuplicateTag(format!("<{name}>"), parser.position())),
156+
}
154157
},
155158
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
156159
};
@@ -177,18 +180,21 @@ fn parse_interconnect(name: &OwnedName,
177180
input,
178181
output,
179182
pack_patterns,
183+
metadata,
180184
})),
181185
"mux" => Ok(Interconnect::Mux(MuxInterconnect {
182186
name: inter_name,
183187
input,
184188
output,
185189
pack_patterns,
190+
metadata,
186191
})),
187192
"complete" => Ok(Interconnect::Complete(CompleteInterconnect {
188193
name: inter_name,
189194
input,
190195
output,
191196
pack_patterns,
197+
metadata,
192198
})),
193199
_ => Err(FPGAArchParseError::InvalidTag(format!("Unknown interconnect tag: {name}"), parser.position())),
194200
}
@@ -257,6 +263,7 @@ fn parse_pb_mode(name: &OwnedName,
257263

258264
let mut pb_types: Vec<PBType> = Vec::new();
259265
let mut interconnects: Option<Vec<Interconnect>> = None;
266+
let mut metadata: Option<Vec<Metadata>> = None;
260267
loop {
261268
match parser.next() {
262269
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
@@ -271,9 +278,10 @@ fn parse_pb_mode(name: &OwnedName,
271278
}
272279
},
273280
"metadata" => {
274-
// TODO: Implement.
275-
// FIXME: Check that this is documented in VTR.
276-
let _ = parser.skip();
281+
metadata = match metadata {
282+
None => Some(parse_metadata(&name, &attributes, parser)?),
283+
Some(_) => return Err(FPGAArchParseError::DuplicateTag(name.to_string(), parser.position())),
284+
}
277285
},
278286
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
279287
};
@@ -302,6 +310,7 @@ fn parse_pb_mode(name: &OwnedName,
302310
name: mode_name,
303311
pb_types,
304312
interconnects,
313+
metadata,
305314
})
306315
}
307316

@@ -367,6 +376,7 @@ fn parse_pb_type(name: &OwnedName,
367376
let mut pb_types: Vec<PBType> = Vec::new();
368377
let mut pb_modes: Vec<PBMode> = Vec::new();
369378
let mut interconnects: Option<Vec<Interconnect>> = None;
379+
let mut metadata: Option<Vec<Metadata>> = None;
370380
loop {
371381
match parser.next() {
372382
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
@@ -417,9 +427,10 @@ fn parse_pb_type(name: &OwnedName,
417427
let _ = parser.skip();
418428
},
419429
"metadata" => {
420-
// TODO: Implement.
421-
// FIXME: Check that this is documented in VTR.
422-
let _ = parser.skip();
430+
metadata = match metadata {
431+
None => Some(parse_metadata(&name, &attributes, parser)?),
432+
Some(_) => return Err(FPGAArchParseError::DuplicateTag(name.to_string(), parser.position())),
433+
}
423434
},
424435
"pinlocations" | "fc" => {
425436
// This one is strange. This should not be in the pb_types.
@@ -462,6 +473,7 @@ fn parse_pb_type(name: &OwnedName,
462473
modes: pb_modes,
463474
pb_types,
464475
interconnects,
476+
metadata,
465477
})
466478
}
467479

fpga_arch_parser/src/parse_layouts.rs

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ use xml::attribute::OwnedAttribute;
99
use crate::parse_error::*;
1010
use crate::arch::*;
1111

12+
use crate::parse_metadata::parse_metadata;
13+
1214
fn parse_grid_location(name: &OwnedName,
1315
attributes: &[OwnedAttribute],
1416
parser: &mut EventReader<BufReader<File>>) -> Result<GridLocation, FPGAArchParseError> {
@@ -123,27 +125,57 @@ fn parse_grid_location(name: &OwnedName,
123125
let end_y_expr = end_y_expr.unwrap_or(String::from("H - 1"));
124126
let incr_y_expr = incr_y_expr.unwrap_or(String::from("h"));
125127

126-
// Skip the contents of the grid location tag.
127-
// TODO: Should parse metadata tag.
128-
let _ = parser.skip();
128+
let mut metadata: Option<Vec<Metadata>> = None;
129+
loop {
130+
match parser.next() {
131+
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
132+
match name.to_string().as_str() {
133+
"metadata" => {
134+
metadata = match metadata {
135+
None => Some(parse_metadata(&name, &attributes, parser)?),
136+
Some(_) => return Err(FPGAArchParseError::DuplicateTag(format!("<{name}>"), parser.position())),
137+
}
138+
},
139+
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
140+
};
141+
},
142+
Ok(XmlEvent::EndElement { name: end_name }) => {
143+
if end_name.to_string() == name.to_string() {
144+
break;
145+
} else {
146+
return Err(FPGAArchParseError::UnexpectedEndTag(name.to_string(), parser.position()));
147+
}
148+
},
149+
Ok(XmlEvent::EndDocument) => {
150+
return Err(FPGAArchParseError::UnexpectedEndOfDocument(name.to_string()));
151+
},
152+
Err(e) => {
153+
return Err(FPGAArchParseError::XMLParseError(format!("{e:?}"), parser.position()));
154+
},
155+
_ => {},
156+
}
157+
};
129158

130159
match name.to_string().as_ref() {
131160
"perimeter" => {
132161
Ok(GridLocation::Perimeter(PerimeterGridLocation {
133162
pb_type,
134163
priority,
164+
metadata,
135165
}))
136166
},
137167
"corners" => {
138168
Ok(GridLocation::Corners(CornersGridLocation {
139169
pb_type,
140170
priority,
171+
metadata,
141172
}))
142173
},
143174
"fill" => {
144175
Ok(GridLocation::Fill(FillGridLocation {
145176
pb_type,
146177
priority,
178+
metadata,
147179
}))
148180
},
149181
"single" => {
@@ -160,6 +192,7 @@ fn parse_grid_location(name: &OwnedName,
160192
priority,
161193
x_expr,
162194
y_expr,
195+
metadata,
163196
}))
164197
},
165198
"col" => {
@@ -170,6 +203,7 @@ fn parse_grid_location(name: &OwnedName,
170203
repeat_x_expr,
171204
start_y_expr,
172205
incr_y_expr,
206+
metadata,
173207
}))
174208
},
175209
"row" => {
@@ -180,6 +214,7 @@ fn parse_grid_location(name: &OwnedName,
180214
incr_x_expr,
181215
start_y_expr,
182216
repeat_y_expr,
217+
metadata,
183218
}))
184219
},
185220
"region" => {
@@ -194,6 +229,7 @@ fn parse_grid_location(name: &OwnedName,
194229
end_y_expr,
195230
repeat_y_expr,
196231
incr_y_expr,
232+
metadata,
197233
}))
198234
},
199235
_ => Err(FPGAArchParseError::InvalidTag(format!("Unknown grid location: {name}"), parser.position())),

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