Merge pull request #52 from AlexandreSinger/feature-parse-arch

[Parse] Added Support for Timing Tags

Author: AlexandreSinger

fpga_arch_parser/src/arch.rs

@@ -371,6 +371,44 @@ pub struct Segment {
     pub switch_points: SegmentSwitchPoints,
 }
 
+pub enum DelayType {
+    Max,
+    Min,
+}
+
+pub enum DelayInfo {
+    Constant {
+        min: f32,
+        max: f32,
+        in_port: String,
+        out_port: String,
+    },
+    Matrix {
+        delay_type: DelayType,
+        // This matrix is [in_pin_idx][out_pin_idx]
+        // TODO: The documentation should be more clear on this.
+        matrix: Vec<Vec<f32>>,
+        in_port: String,
+        out_port: String,
+    },
+}
+
+pub enum TimingConstraintType {
+    Hold,
+    Setup,
+    ClockToQ,
+}
+
+pub struct TimingConstraintInfo {
+    pub constraint_type: TimingConstraintType,
+    // NOTE: Only ClockToQ can have two different min/max values right now.
+    //       A bit of future proofing and cleanup to split max and min here.
+    pub min_value: f32,
+    pub max_value: f32,
+    pub port: String,
+    pub clock: String,
+}
+
 pub struct PackPattern {
     pub name: String,
     pub in_port: String,
@@ -385,6 +423,7 @@ pub struct CompleteInterconnect {
     //        may be a single pack pattern; however, an interconnect may have many
     //        pack patterns.
     pub pack_patterns: Vec<PackPattern>,
+    pub delays: Vec<DelayInfo>,
     pub metadata: Option<Vec<Metadata>>,
 }
 
@@ -393,6 +432,7 @@ pub struct DirectInterconnect {
     pub input: String,
     pub output: String,
     pub pack_patterns: Vec<PackPattern>,
+    pub delays: Vec<DelayInfo>,
     pub metadata: Option<Vec<Metadata>>,
 }
 
@@ -401,6 +441,7 @@ pub struct MuxInterconnect {
     pub input: String,
     pub output: String,
     pub pack_patterns: Vec<PackPattern>,
+    pub delays: Vec<DelayInfo>,
     pub metadata: Option<Vec<Metadata>>,
 }
 
@@ -433,6 +474,8 @@ pub struct PBType {
     pub modes: Vec<PBMode>,
     pub pb_types: Vec<PBType>,
     pub interconnects: Vec<Interconnect>,
+    pub delays: Vec<DelayInfo>,
+    pub timing_constraints: Vec<TimingConstraintInfo>,
     pub metadata: Option<Vec<Metadata>>,
 }
 

fpga_arch_parser/src/lib.rs

@@ -16,12 +16,12 @@ mod parse_layouts;
 mod parse_device;
 mod parse_switch_list;
 mod parse_segment_list;
+mod parse_timing;
 mod parse_complex_block_list;
 
 pub use crate::parse_error::FPGAArchParseError;
 pub use crate::arch::*;
 
-use crate::parse_port::parse_port;
 use crate::parse_tiles::parse_tiles;
 use crate::parse_layouts::parse_layouts;
 use crate::parse_device::parse_device;

fpga_arch_parser/src/parse_complex_block_list.rs

@@ -9,8 +9,13 @@ use xml::attribute::OwnedAttribute;
 use crate::parse_error::*;
 use crate::arch::*;
 
-use crate::parse_port;
+use crate::parse_port::parse_port;
 use crate::parse_metadata::parse_metadata;
+use crate::parse_timing::parse_delay_constant;
+use crate::parse_timing::parse_delay_matrix;
+use crate::parse_timing::parse_t_setup;
+use crate::parse_timing::parse_t_hold;
+use crate::parse_timing::parse_clock_to_q;
 
 fn parse_pack_pattern(name: &OwnedName,
                       attributes: &[OwnedAttribute],
@@ -131,6 +136,7 @@ fn parse_interconnect(name: &OwnedName,
     };
 
     let mut pack_patterns: Vec<PackPattern> = Vec::new();
+    let mut delays: Vec<DelayInfo> = Vec::new();
     let mut metadata: Option<Vec<Metadata>> = None;
     loop {
         match parser.next() {
@@ -140,14 +146,10 @@ fn parse_interconnect(name: &OwnedName,
                         pack_patterns.push(parse_pack_pattern(&name, &attributes, parser)?);
                     },
                     "delay_constant" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        delays.push(parse_delay_constant(&name, &attributes, parser)?);
                     },
                     "delay_matrix" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        delays.push(parse_delay_matrix(&name, &attributes, parser)?);
                     },
                     "metadata" => {
                         metadata = match metadata {
@@ -180,20 +182,23 @@ fn parse_interconnect(name: &OwnedName,
             input,
             output,
             pack_patterns,
+            delays,
             metadata,
         })),
         "mux" => Ok(Interconnect::Mux(MuxInterconnect {
             name: inter_name,
             input,
             output,
             pack_patterns,
+            delays,
             metadata,
         })),
         "complete" => Ok(Interconnect::Complete(CompleteInterconnect {
             name: inter_name,
             input,
             output,
             pack_patterns,
+            delays,
             metadata,
         })),
         _ => Err(FPGAArchParseError::InvalidTag(format!("Unknown interconnect tag: {name}"), parser.position())),
@@ -376,6 +381,8 @@ fn parse_pb_type(name: &OwnedName,
     let mut pb_types: Vec<PBType> = Vec::new();
     let mut pb_modes: Vec<PBMode> = Vec::new();
     let mut interconnects: Option<Vec<Interconnect>> = None;
+    let mut delays: Vec<DelayInfo> = Vec::new();
+    let mut timing_constraints: Vec<TimingConstraintInfo> = Vec::new();
     let mut metadata: Option<Vec<Metadata>> = None;
     loop {
         match parser.next() {
@@ -402,29 +409,19 @@ fn parse_pb_type(name: &OwnedName,
                         let _ = parser.skip();
                     },
                     "delay_constant" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        delays.push(parse_delay_constant(&name, &attributes, parser)?);
                     },
                     "delay_matrix" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        delays.push(parse_delay_matrix(&name, &attributes, parser)?);
                     },
                     "T_setup" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        timing_constraints.push(parse_t_setup(&name, &attributes, parser)?);
                     },
                     "T_hold" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        timing_constraints.push(parse_t_hold(&name, &attributes, parser)?);
                     },
                     "T_clock_to_Q" => {
-                        // TODO: Implement.
-                        // FIXME: Check that this is documented in VTR.
-                        let _ = parser.skip();
+                        timing_constraints.push(parse_clock_to_q(&name, &attributes, parser)?);
                     },
                     "metadata" => {
                         metadata = match metadata {
@@ -473,6 +470,8 @@ fn parse_pb_type(name: &OwnedName,
         modes: pb_modes,
         pb_types,
         interconnects,
+        delays,
+        timing_constraints,
         metadata,
     })
 }

fpga_arch_parser/src/parse_tiles.rs

@@ -9,7 +9,7 @@ use xml::attribute::OwnedAttribute;
 use crate::parse_error::*;
 use crate::arch::*;
 
-use crate::parse_port;
+use crate::parse_port::parse_port;
 
 fn parse_tile_site(name: &OwnedName,
                    attributes: &[OwnedAttribute],