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Merged
AlexandreSinger merged 1 commit into from
Dec 4, 2025
Merged

[Parse] Added Metadata Parsing #51

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17 changes: 17 additions & 0 deletions fpga_arch_parser/src/arch.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,11 @@ pub struct Model {

}

pub struct Metadata {
pub name: String,
pub value: String,
}

pub enum PinEquivalence {
None,
Full,
Expand Down Expand Up @@ -137,23 +142,27 @@ pub struct Tile {
pub struct FillGridLocation {
pub pb_type: String,
pub priority: i32,
pub metadata: Option<Vec<Metadata>>,
}

pub struct PerimeterGridLocation {
pub pb_type: String,
pub priority: i32,
pub metadata: Option<Vec<Metadata>>,
}

pub struct CornersGridLocation {
pub pb_type: String,
pub priority: i32,
pub metadata: Option<Vec<Metadata>>,
}

pub struct SingleGridLocation {
pub pb_type: String,
pub priority: i32,
pub x_expr: String,
pub y_expr: String,
pub metadata: Option<Vec<Metadata>>,
}

pub struct ColGridLocation {
Expand All @@ -163,6 +172,7 @@ pub struct ColGridLocation {
pub repeat_x_expr: Option<String>,
pub start_y_expr: String,
pub incr_y_expr: String,
pub metadata: Option<Vec<Metadata>>,
}

pub struct RowGridLocation {
Expand All @@ -172,6 +182,7 @@ pub struct RowGridLocation {
pub incr_x_expr: String,
pub start_y_expr: String,
pub repeat_y_expr: Option<String>,
pub metadata: Option<Vec<Metadata>>,
}

pub struct RegionGridLocation {
Expand All @@ -185,6 +196,7 @@ pub struct RegionGridLocation {
pub end_y_expr: String,
pub repeat_y_expr: Option<String>,
pub incr_y_expr: String,
pub metadata: Option<Vec<Metadata>>,
}

pub enum GridLocation {
Expand Down Expand Up @@ -373,20 +385,23 @@ pub struct CompleteInterconnect {
// may be a single pack pattern; however, an interconnect may have many
// pack patterns.
pub pack_patterns: Vec<PackPattern>,
pub metadata: Option<Vec<Metadata>>,
}

pub struct DirectInterconnect {
pub name: String,
pub input: String,
pub output: String,
pub pack_patterns: Vec<PackPattern>,
pub metadata: Option<Vec<Metadata>>,
}

pub struct MuxInterconnect {
pub name: String,
pub input: String,
pub output: String,
pub pack_patterns: Vec<PackPattern>,
pub metadata: Option<Vec<Metadata>>,
}

pub enum Interconnect {
Expand All @@ -399,6 +414,7 @@ pub struct PBMode {
pub name: String,
pub pb_types: Vec<PBType>,
pub interconnects: Vec<Interconnect>,
pub metadata: Option<Vec<Metadata>>,
}

pub enum PBTypeClass {
Expand All @@ -417,6 +433,7 @@ pub struct PBType {
pub modes: Vec<PBMode>,
pub pb_types: Vec<PBType>,
pub interconnects: Vec<Interconnect>,
pub metadata: Option<Vec<Metadata>>,
}

pub struct FPGAArch {
Expand Down
1 change: 1 addition & 0 deletions fpga_arch_parser/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ use xml::attribute::OwnedAttribute;

mod arch;
mod parse_error;
mod parse_metadata;
mod parse_port;
mod parse_tiles;
mod parse_layouts;
Expand Down
30 changes: 21 additions & 9 deletions fpga_arch_parser/src/parse_complex_block_list.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ use crate::parse_error::*;
use crate::arch::*;

use crate::parse_port;
use crate::parse_metadata::parse_metadata;

fn parse_pack_pattern(name: &OwnedName,
attributes: &[OwnedAttribute],
Expand Down Expand Up @@ -130,6 +131,7 @@ fn parse_interconnect(name: &OwnedName,
};

let mut pack_patterns: Vec<PackPattern> = Vec::new();
let mut metadata: Option<Vec<Metadata>> = None;
loop {
match parser.next() {
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
Expand All @@ -148,9 +150,10 @@ fn parse_interconnect(name: &OwnedName,
let _ = parser.skip();
},
"metadata" => {
// TODO: Implement.
// FIXME: Check that this is documented in VTR.
let _ = parser.skip();
metadata = match metadata {
None => Some(parse_metadata(&name, &attributes, parser)?),
Some(_) => return Err(FPGAArchParseError::DuplicateTag(format!("<{name}>"), parser.position())),
}
},
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
};
Expand All @@ -177,18 +180,21 @@ fn parse_interconnect(name: &OwnedName,
input,
output,
pack_patterns,
metadata,
})),
"mux" => Ok(Interconnect::Mux(MuxInterconnect {
name: inter_name,
input,
output,
pack_patterns,
metadata,
})),
"complete" => Ok(Interconnect::Complete(CompleteInterconnect {
name: inter_name,
input,
output,
pack_patterns,
metadata,
})),
_ => Err(FPGAArchParseError::InvalidTag(format!("Unknown interconnect tag: {name}"), parser.position())),
}
Expand Down Expand Up @@ -257,6 +263,7 @@ fn parse_pb_mode(name: &OwnedName,

let mut pb_types: Vec<PBType> = Vec::new();
let mut interconnects: Option<Vec<Interconnect>> = None;
let mut metadata: Option<Vec<Metadata>> = None;
loop {
match parser.next() {
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
Expand All @@ -271,9 +278,10 @@ fn parse_pb_mode(name: &OwnedName,
}
},
"metadata" => {
// TODO: Implement.
// FIXME: Check that this is documented in VTR.
let _ = parser.skip();
metadata = match metadata {
None => Some(parse_metadata(&name, &attributes, parser)?),
Some(_) => return Err(FPGAArchParseError::DuplicateTag(name.to_string(), parser.position())),
}
},
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
};
Expand Down Expand Up @@ -302,6 +310,7 @@ fn parse_pb_mode(name: &OwnedName,
name: mode_name,
pb_types,
interconnects,
metadata,
})
}

Expand Down Expand Up @@ -367,6 +376,7 @@ fn parse_pb_type(name: &OwnedName,
let mut pb_types: Vec<PBType> = Vec::new();
let mut pb_modes: Vec<PBMode> = Vec::new();
let mut interconnects: Option<Vec<Interconnect>> = None;
let mut metadata: Option<Vec<Metadata>> = None;
loop {
match parser.next() {
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
Expand Down Expand Up @@ -417,9 +427,10 @@ fn parse_pb_type(name: &OwnedName,
let _ = parser.skip();
},
"metadata" => {
// TODO: Implement.
// FIXME: Check that this is documented in VTR.
let _ = parser.skip();
metadata = match metadata {
None => Some(parse_metadata(&name, &attributes, parser)?),
Some(_) => return Err(FPGAArchParseError::DuplicateTag(name.to_string(), parser.position())),
}
},
"pinlocations" | "fc" => {
// This one is strange. This should not be in the pb_types.
Expand Down Expand Up @@ -462,6 +473,7 @@ fn parse_pb_type(name: &OwnedName,
modes: pb_modes,
pb_types,
interconnects,
metadata,
})
}

Expand Down
42 changes: 39 additions & 3 deletions fpga_arch_parser/src/parse_layouts.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ use xml::attribute::OwnedAttribute;
use crate::parse_error::*;
use crate::arch::*;

use crate::parse_metadata::parse_metadata;

fn parse_grid_location(name: &OwnedName,
attributes: &[OwnedAttribute],
parser: &mut EventReader<BufReader<File>>) -> Result<GridLocation, FPGAArchParseError> {
Expand Down Expand Up @@ -123,27 +125,57 @@ fn parse_grid_location(name: &OwnedName,
let end_y_expr = end_y_expr.unwrap_or(String::from("H - 1"));
let incr_y_expr = incr_y_expr.unwrap_or(String::from("h"));

// Skip the contents of the grid location tag.
// TODO: Should parse metadata tag.
let _ = parser.skip();
let mut metadata: Option<Vec<Metadata>> = None;
loop {
match parser.next() {
Ok(XmlEvent::StartElement { name, attributes, .. }) => {
match name.to_string().as_str() {
"metadata" => {
metadata = match metadata {
None => Some(parse_metadata(&name, &attributes, parser)?),
Some(_) => return Err(FPGAArchParseError::DuplicateTag(format!("<{name}>"), parser.position())),
}
},
_ => return Err(FPGAArchParseError::InvalidTag(name.to_string(), parser.position())),
};
},
Ok(XmlEvent::EndElement { name: end_name }) => {
if end_name.to_string() == name.to_string() {
break;
} else {
return Err(FPGAArchParseError::UnexpectedEndTag(name.to_string(), parser.position()));
}
},
Ok(XmlEvent::EndDocument) => {
return Err(FPGAArchParseError::UnexpectedEndOfDocument(name.to_string()));
},
Err(e) => {
return Err(FPGAArchParseError::XMLParseError(format!("{e:?}"), parser.position()));
},
_ => {},
}
};

match name.to_string().as_ref() {
"perimeter" => {
Ok(GridLocation::Perimeter(PerimeterGridLocation {
pb_type,
priority,
metadata,
}))
},
"corners" => {
Ok(GridLocation::Corners(CornersGridLocation {
pb_type,
priority,
metadata,
}))
},
"fill" => {
Ok(GridLocation::Fill(FillGridLocation {
pb_type,
priority,
metadata,
}))
},
"single" => {
Expand All @@ -160,6 +192,7 @@ fn parse_grid_location(name: &OwnedName,
priority,
x_expr,
y_expr,
metadata,
}))
},
"col" => {
Expand All @@ -170,6 +203,7 @@ fn parse_grid_location(name: &OwnedName,
repeat_x_expr,
start_y_expr,
incr_y_expr,
metadata,
}))
},
"row" => {
Expand All @@ -180,6 +214,7 @@ fn parse_grid_location(name: &OwnedName,
incr_x_expr,
start_y_expr,
repeat_y_expr,
metadata,
}))
},
"region" => {
Expand All @@ -194,6 +229,7 @@ fn parse_grid_location(name: &OwnedName,
end_y_expr,
repeat_y_expr,
incr_y_expr,
metadata,
}))
},
_ => Err(FPGAArchParseError::InvalidTag(format!("Unknown grid location: {name}"), parser.position())),
Expand Down
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