This updated analysis evaluates the Time and Space Complexity of the NETS project following the implementation of unified solver logic and optimized backtracking, dynamic programming, and divide-and-conquer strategies.
Variables Used:
-
$N$ : Total number of tiles on the board ($N = \text{Rows} \times \text{Cols}$ ). -
$W$ : Width of the board. -
$k$ : Maximum number of rotations per tile ($k=4$ ).
| Algorithm | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| Backtracking (solve_bt) | Uses Minimum Remaining Values (MRV) heuristic and early pruning. Highly effective for smaller grids. |
| Algorithm | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| DP Solver (solve_dp) | Optimized row-major traversal with memoized frontier state. Most efficient for boards with small width |
| Algorithm | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| D&C Solver (solve_dac) | Recursive region-splitting with boundary-matching. Reduces effective search space on structured grids. |
| Function | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| sortTiles_dac | Classic Divide and Conquer sorting algorithm used to prioritize tiles by constraint degree. |
| Function | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| sortMoves_greedy | Quick Sort algorithm for CPU move prioritization based on local fit heuristics. |
| Function | Time Complexity | Space Complexity | Notes |
|---|---|---|---|
| isSolved | Verifies win condition (connectivity, acyclicity, loose ends) using optimized DFS traversal with integer-indexed adjacency lists and |
Port matching and constraint evaluation have been moved from vector-based list comparisons to uint8_t bitmask operations. This allows the solvers to perform rotation compatibility checks in constant time ($O(1)$) with zero memory allocations in the core search loop.
The board representation was migrated from a 2D vector<vector<Tile>> to a flattened 1D vector<Tile>. This optimization:
- Improves Cache Locality: Tiles are contiguous in memory, reducing CPU cache misses during traversal.
- Reduces Overhead: Minimizes memory management overhead when copying the board for move evaluation.
The graph structure now uses a flattened std::vector for adjacency storage instead of a std::map. This removes the
By centralizing port mask calculation in SolverUtils.hpp, all solvers now share a consistent, high-performance logic for rotation evaluation.
The use of Merge Sort (Divide and Conquer) to order tiles by their constraint degree (degree + adjacency to boundaries) allows the recursive solvers (BT and DAC) to prune search branches much earlier, avoiding
The DP solver effectively manages the state-space search by only storing the necessary boundary information ("frontier"), leading to linear-time complexity with respect to the number of rows for a fixed width. For wrapping boards, it iterates through all boundary configurations, resulting in
| Paradigm | Algorithm | Best For | Typical Time | Typical Space |
|---|---|---|---|---|
| Greedy | CPU Strategy | Real-time moves | ||
| Backtracking | BT Solver | Small/Medium grids |
|
|
| DP | DP Solver | Small width ( |
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| DP (Wrapping) | DP Solver | Toroidal grids | ||
| Divide & Conquer | DAC Solver | Large structured grids |
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|
| Sorting (D&C) | Merge Sort | Tile prioritization | ||
| Sorting | Quick Sort | Move selection | ||
| Traversal | DFS | Win condition checks |