@@ -406,7 +406,9 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
406406 RegisterTest ( tests, " f32 floor" , []( TestRegf32 a ) { return FS::Floor ( a ); } );
407407 RegisterTest ( tests, " f32 trunc" , []( TestRegf32 a ) { return FS::Trunc ( a ); } );
408408 RegisterTest ( tests, " f32 signbit" , []( TestRegf32 a, TestRegf32 b ) { return FS::SignBit ( a ) ^ b; } );
409- // RegisterTest( tests, "f32 modulus", []( TestRegf32 a, TestRegf32 b ) { return FS::Modulus( a, b ); } );
409+ #if !FASTSIMD_IS_RELAXED
410+ RegisterTest ( tests, " f32 modulus" , []( TestRegf32 a, TestRegf32 b ) { return FS::Modulus ( a, b ); } );
411+ #endif
410412
411413 RegisterTest ( tests, " f32 sqrt" , []( TestRegf32 a ) { return FS::Sqrt ( FS::Min ( FS::Max ( FS::Abs ( a ), TestRegf32 ( 1 .e -16f ) ), TestRegf32 ( 1 .e +16f ) ) ); } );
412414 RegisterTest ( tests, " f32 inv sqrt" , []( TestRegf32 a ) { return FS::InvSqrt ( FS::Min ( FS::Max ( FS::Abs ( a ), TestRegf32 ( 1 .e -16f ) ), TestRegf32 ( 1 .e +16f ) ) ); } ).relaxedAccuracy = 8192 ;
@@ -422,7 +424,7 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
422424 RegisterTest ( tests, " f32 pow" , []( TestRegf32 a, TestRegf32 b ) { return FS::Pow ( a, b ); } ).relaxedAccuracy = 8192 ;
423425
424426 RegisterTest ( tests, " i32 convert to f32" , []( TestRegi32 a ) { return FS::Convert<float >( a ); } );
425- RegisterTest ( tests, " f32 convert to i32" , []( TestRegf32 a ) { return FS::Convert<int32_t >( FS::Min ( FS::Max ( a, TestRegf32 ( -2147483648 ) ), TestRegf32 ( 2147483520 ) ) ); } );
427+ RegisterTest ( tests, " f32 convert to i32" , []( TestRegf32 a ) { return FS::Convert<int32_t >( FS::Min ( FS::Max ( a, TestRegf32 ( -2147483647 - 1 ) ), TestRegf32 ( 2147483520 ) ) ); } );
426428
427429 RegisterTest ( tests, " f32 cast to i32" , []( TestRegf32 a ) { return FS::Cast<int32_t >( a ); } );
428430 RegisterTest ( tests, " i32 cast to f32" , []( TestRegi32 a ) { return FS::Cast<float >( a ); } );
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