rstdoc: update change logs, avx512 flag topics

Author: pinterf

distrib/docs/english/source/avisynthdoc/FilterSDK/Cplusplus_api.rst

@@ -487,7 +487,10 @@ To test against the default Avisynth+ "fast" flags, test:
 ::
 
     if ((env->GetCPUFlags() & CPUF_AVX512_FAST) == CPUF_AVX512_FAST) {
-        // all "fast" AVX512 features supported
+        // all "fast" AVX512 features supported (in AviSynth: *_avx512.cpp)
+        // function dispatch here
+    } else if ((env->GetCPUFlags() & CPUF_AVX512_BASE) == CPUF_AVX512_BASE)) {
+        // "base" AVX512 features supported (in AviSynth: *_avx512b.cpp)
         // function dispatch here
     } else if (env->GetCPUFlags() & CPUF_AVX2) {
         // AVX2 path
@@ -497,13 +500,27 @@ To test against the default Avisynth+ "fast" flags, test:
         // simple C++ path
     }
 
-In Avisynth - as of end of 2025 -, the AVX512 function dispatchers check for CPUF_AVX512_FAST for calling function from ``*_avx512.cpp`` files.
-Compiler flags for ``*_avx512.cpp`` files are automatically set for MSVC as /arch:AVX512.
-For gcc or LLVM (clang-cl) builds the relevant flags in CMakeLists.txt are set
-as ``"-mfma -mavx512f -mavx512cd -mavx512bw -mavx512dq -mavx512vl -mavx512vnni -mavx512vbmi -mavx512vbmi2 -mavx512bitalg -mavx512vpopcntdq "`` .
+In Avisynth AVX512 function dispatchers check for CPUF_AVX512_BASE and CPUF_AVX512_FAST for calling function from 
+``*_avx512b.cpp`` or ``*_avx512.cpp`` files, repectively.
+
+Compiler flags for ``*_avx512b.cpp`` and ``*_avx512.cpp`` files are automatically set for MSVC as ``/arch:AVX512``.
+
+For gcc or LLVM (clang-cl) builds the relevant flags in CMakeLists.txt are set as
+
+* "Base" (``*_avx512b.cpp``) : ``" -mfma -mbmi2 -mavx512f -mavx512cd -mavx512bw -mavx512dq -mavx512vl "``
+* "Fast" (``*_avx512.cpp``) : ``" -mfma -mbmi2 -mavx512f -mavx512cd -mavx512bw -mavx512dq -mavx512vl -mavx512vnni -mavx512vbmi -mavx512vbmi2 -mavx512bitalg -mavx512vpopcntdq "``
+
+Similar to AVX2, FMA must be added explicitly for GCC/Clang. We also enable BMI2, as it is standard since AVX2 and useful for 
+AVX512 mask operations like _bzhi_u64/u32. The core subsets (F, CD, BW, DQ, VL) comprising the CPUF_AVX512_BASE 
+flag are present on all AVX-512-capable architectures.
+
+We note again: early Xeon (e.g., Skylake-X/Cascadelake) may exhibit severe thermal throttling even on a single thread. 
+In AviSynth+, AVX512_BASE must be manually enabled in-script unless ``CPUF_AVX512_FAST`` is also detected.
+Functions in ``*_avx512b.cpp`` should be dispatched on ``CPUF_AVX512_BASE``.
+Functions in ``*_avx512.cpp`` should be dispatched on ``CPUF_AVX512_FAST``.
 
-The relevant CPU features for the "Fast" group are: FMA3, AVX512_BASE (F, CD, BW, DQ, Vl) and the "fast avx512" criteria.
 AVX512 is considered to be "Fast" when either 
+
 - pre AVX10, and minimum Ice Lake architecture is found (VNNI, VBMI, VBMI2, BITALG, VPOPCNTDQ and three crypto flags).
 - or AVX10 (any version) is found.
 
@@ -2909,7 +2926,7 @@ Intel x86 and AMD64 CPU feature flags
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
    | ``CPUF_AVX512VBMI``          | ``0x10000000``     | AVX-512 VBMI, byte/word shuffling, sign/zero extension, and general pixel manipulation                                    |
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
-   | ``CPUF_AVX512_BASE``         | ``0x20000000``     | AVX-512 Base group feature set. When F, CD, BW, DQ, VL flags exist                                                        |
+   | ``CPUF_AVX512_BASE``         | ``0x20000000``     | AVX-512 Base group feature set. When F, CD, BW, DQ, VL flags exist. Avisynth sets it only if CPUF_AVX512_FAST exists      |
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
    | ``CPUF_AVX512_FAST``         | ``0x40000000``     | Base + VNNI, VBMI, VBMI2, BITALG, VPOPCNTDQ. Spec detection logic excludes older/throttling models that also have these   |
    |                              |                    | features                                                                                                                  |
@@ -2934,6 +2951,11 @@ AVX-512 features are grouped into two categories:
 - CPUF_AVX512_BASE: Base (F, CD, BW, DQ, VL)
 - CPUF_AVX512_FAST: The "usable" AVX-512, starting with Intel's 10th gen Ice Lake, incl. AMD Zen4/5. The features Base + (VNNI, VBMI, VBMI2, BITALG, VPOPCNTDQ) are guaranteed.
 
+Important note for user of old AVX512 CPUs, where only the Base flags exist (not an Ice Lake or better level CPU): 
+the "Base" group flag ``CPUF_AVX512_BASE`` is not enabled automatically, even if the individual base flags exist!
+The reason is to prevent the AVX512 Base-only optimizations in Avisynth for possibly old AVX512 systems.
+However when users know what they are doing (know they do have non-throttling old CPU), they can enable it with ``SetMaxCPU("avx512base+")``
+
 "Fast" means a usable AVX-512 implementation without severe throttling penalties on client CPUs. It basically guarantees a feature set 
 similar to Intel Ice Lake/Rocket Lake and AMD Zen4/Zen5 and excludes older AVX-512 implementations (Skylake-X, Cascade Lake, Ice Lake-SP) 
 which have severe throttling issues on client CPUs.
@@ -2953,7 +2975,7 @@ Due to the large number of AVX-512 sub-features, the following group and composi
    :align: center
 
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
-   | ``CPUF_AVX512_BASE``         | ``0x20000000``     | AVX-512 Base group feature set. When F, CD, BW, DQ, VL flags exist                                                        |
+   | ``CPUF_AVX512_BASE``         | ``0x20000000``     | AVX-512 Base group feature set. When F, CD, BW, DQ, VL flags. Avisynth sets it only if CPUF_AVX512_FAST exists            |
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
    | ``CPUF_AVX512_FAST``         | ``0x40000000``     | AVX-512 Advance group FAST (Ice Lake/Rocket Lake/Zen4/Zen5) feature set: Base + VNNI, VBMI, VBMI2, BITALG, VPOPCNTDQ.     |
    +------------------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------+
@@ -2973,7 +2995,10 @@ Due to the large number of AVX-512 sub-features, the following group and composi
     Compiling code solely with checking only ``"avx512base"`` (which often only implies first-generation AVX-512) 
     can lead to poor performance due to aggressive clock throttling on older hardware.
 
-    Developers should generally use ``"avx512fast"`` group as a minimum for realistic performance testing of 512-bit code paths.
+    Developers should generally use ``"avx512fast"`` group in their optimizer function dispatchers, as a minimum for 
+    realistic performance testing of 512-bit code paths. Avisynth (e.g. in resamplers) has both base and fast optimizations
+    implemented. However for accessing the optimizations for "Base" AVX512 on old CPUs, ``SetMaxCPU("avx512base+")`` script 
+    command must be used to re-enable AVX512 on these systems.
 
 
 .. note::

distrib/docs/english/source/avisynthdoc/changelist376.rst

@@ -13,7 +13,8 @@ Additions, changes
 - "Info": Optimize AVX512 features display, group features, make a bit more compact
 - "Info": add L2 cache size display
 - "SetMaxCPU": add "avx512base" and "avx512fast" options to enable/disable AVX512 grouped features.
-  see :ref:`SetMaxCPU <setmaxcpu>` .
+  see :ref:`SetMaxCPU <setmaxcpu>` . Users of base-only AVX512 CPUs can enable Avisynth-optimizations
+  with SetMaxCPU("avx512base+").
 - ARM64 (aarch64) area:
 
   * "Info": add ARMV8-A features display (NEON, DOTPROD, SVE2)
@@ -27,10 +28,11 @@ Additions, changes
 Build environment, Interface
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 - introduce ``AVS_RESTRICT`` to ``avs/config.h`` (compiler invariant c++ ``__restrict``)
-- AVX512: CMake to recognize ``*_avx512.*`` file pattern, add compiler specific AVX512 
+- AVX512: CMake to recognize ``*_avx512b.*`` and ``*_avx512.*`` file pattern, add compiler specific AVX512 
   compile flags accordingly (AVX512 Base and Ice Lake extensions)
 - AVX512 support by conditional define.
   Define `INTEL_INTRINSICS_AVX512` if avx512 modules are enabled and compiler supports it.
+  For MSVC,AVX512 support enabled only from MSVC 2019 16.2 (19.22) or newer.
 - add ``.editorconfig``, update .gitignore to include the new .slnx format of Visual Studio 2026
 - v12 interface: Global Lock support (https://github.com/AviSynth/AviSynthPlus/issues/444), 
   mainly for plugins using common fftw3 library:
@@ -55,7 +57,7 @@ Build environment, Interface
   - added many new AVX512 individual feature flags
   - added ARM64 feature flags CPUF_ARM_NEON, CPUF_ARM_DOTPROD, CPUF_ARM_SVE2
   - CPUF_xxxxx flags are now 64 bit, replace enum with constexpr.
-- CMakeLists.txt: avx512 compile flag support for gcc/clang ("fast" Ice Lake-like feature set).
+- CMakeLists.txt: avx512 compile flag support for gcc/clang ("base" and "fast", latter is Ice Lake-like feature set).
 - V12 interface: ``GetCPUFlagsEx`` returning 64 bit flags (too many AVX512 subfeatures to fit in 32 bit).
   C interface: ``avs_get_cpu_flags_ex``.
   see :ref:`GetCPUFlagsEx<cplusplus_getcpuflagsex>` and :ref:`GetCPUFlags<cplusplus_getcpuflags>`
@@ -111,20 +113,20 @@ Bugfixes
 
 Optimizations
 ~~~~~~~~~~~~~
+- TurnLeft, TurnRight: AVX2 support (1,5-3x speed on i7-11700 compared to SSE2 version)
+- Turn180 AVX2 support (very slight speed gain)
 - Resamplers: 
 
   * introduce a SIMD-like C header (avs_simd_c.h) for smart auto-vectorizing compilers.
   * restore vertical float performance (3.7.4 was slower than 3.7.3) + SSE2 special optimization
   * further optimize verticals, use ``AVS_RESTRICT``
+  * (quicker RGB32/64 horizontal on AVX2 since TurnRigh/Left was optimized - packed RGB H-resize = TurnLeft-V-Resize-TurnRight)
   * optimize SSSE3 and AVX2 horizontal resampler for 32-bit float for small (<=4) kernel sizes
   * optimize 32-bit float vertical avx2
   * add AVX512 code path 
 
     - 32-bit float resamplers, verticals; horizontals up to kernel size 16.
-    - 8-16-bit horizontal resamplers,
-
-      - kernel size <= 4 and specific ratios; 300%+ !!
-      - kernel sizes up to 8 and 16 and specific ratios.
+    - 8-16-bit horizontal resamplers, for kernel size <= 16 and specific ratios; speed gain up to 300%+ (DTL2020)!!
     - 8-16-bit vertical resamplers
   * (Work In Progress) unify horizontal and vertical plane processing flow
 
@@ -151,7 +153,7 @@ Documentation
 Please report bugs at `github AviSynthPlus page`_ - or - `Doom9's AviSynth+
 forum`_
 
-$Date: 2026/01/07 15:19:00 $
+$Date: 2026/01/17 21:50:00 $
 
 .. _github AviSynthPlus page:
     https://github.com/AviSynth/AviSynthPlus

distrib/docs/english/source/avisynthdoc/syntax/syntax_internal_functions_global_options.rst

@@ -105,7 +105,7 @@ distinguishing the Ice Lake generation from the earlier Skylake-X and Cascade La
 Multiple options can be put in a comma separated list. They will evaluate in that order. 
 
 The ``"avx512base"`` and ``"avx512fast"`` cover a group of feature flags. Internal Avisynth+ codes test for 
-``CPUF_AVX512_FAST`` in internal AVX-512 optimized paths, not the base CPUF_AVX512_BASE one.
+``CPUF_AVX512_BASE`` and ``CPUF_AVX512_FAST`` in internal AVX-512 optimized paths.
 
 .. note::
 
@@ -123,6 +123,9 @@ The ``"avx512base"`` and ``"avx512fast"`` cover a group of feature flags. Intern
     lead to **misleadingly poor performance** due to aggressive clock throttling on older hardware.
 
     Developers should generally use the ``"avx512fast"`` group for realistic performance testing of 512-bit code paths.
+    
+    Users, who have AVX512 Base level CPU but "Fast" is not fulfilled, must manually enable the Base features,
+    despite that the individual flags (F, CD, BW, DQ, VL) may exist.
 
 
 *Examples:*
@@ -131,6 +134,7 @@ The ``"avx512base"`` and ``"avx512fast"`` cover a group of feature flags. Intern
     SetMaxCPU("SSE2") #reports at most SSE2 processor (even if AVX2 is available)
     SetMaxCPU("avx,sse4.1-") #limits to avx2 but explicitely removes reporting sse4.1 support
     SetMaxCPU("none,avx2+") #limits to plain C, then switches on AVX2-only support
+    SetMaxCPU("avx512base+") # Forcibly switches on AVX512 Base support, for users of old AVX512 CPU.
 
 OnCPU
 ~~~~~