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Add VectorFIFOF module
The VectorFIFOF module has a FIFOF interface for enqueuing and dequeuing data. It also provides a method, which returns a Vector of Maybe entries, to access all entries in the queue simultaneously. Co-authored-by: Julie Schwartz <quark@bluespec.com>
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‎Libraries/Misc/Makefile‎

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$(BSC) -u $(BSCFLAGS) EdgeFIFOFs.bsv
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$(BSC) -u $(BSCFLAGS) GetPut_Aux.bsv
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$(BSC) -u $(BSCFLAGS) Semi_FIFOF.bsv
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$(BSC) -u $(BSCFLAGS) VectorFIFOF.bsv
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.PHONY: clean full_clean
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clean full_clean:

‎Libraries/Misc/VectorFIFOF.bsv‎

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// Copyright (c) 2025 Bluespec, Inc.
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//
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// SPDX-License-Identifier: BSD-3-Clause
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package VectorFIFOF;
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// This package implements a fifo like module with a parameterized
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// depth and standard FIFOF interface. The module also provides
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// parallel access to all items in the fifo, for example, to allow
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// searching for hazards before enqueueing new items.
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//
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// The enq, deq, and clear methods may be called in any order. enq
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// and deq may not occur in the same cycle if the fifo is empty or
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// full.
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import FIFOF ::*;
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import RevertingVirtualReg ::*;
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import Vector ::*;
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interface VectorFIFOF#(numeric type depth, type t);
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interface FIFOF#(t) fifo;
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method Vector#(depth, Maybe#(t)) vector();
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endinterface
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module mkVectorFIFOF(VectorFIFOF#(depth, t))
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provisos(
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Bits#(t, tsz)
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);
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Vector#(depth, Reg#(t)) vr_data <- replicateM(mkRegU);
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Reg#(UInt#(TLog#(TAdd#(depth,1)))) r_count <- mkReg(0);
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RWire#(t) w_enq <- mkRWire;
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PulseWire pw_deq <- mkPulseWire;
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PulseWire pw_clear <- mkPulseWire;
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(* fire_when_enabled, no_implicit_conditions *)
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rule rl_magic;
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if (pw_clear)
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r_count <= 0;
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else if (isValid(w_enq.wget) && !pw_deq)
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r_count <= r_count + 1;
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else if (!isValid(w_enq.wget) && pw_deq)
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r_count <= r_count - 1;
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Vector#(depth, t) newdata = readVReg(vr_data);
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if (pw_deq)
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for (Integer i = 0; i < fromInteger(valueOf(depth)) - 1; i = i + 1)
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newdata[i] = newdata[i + 1];
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if (w_enq.wget matches tagged Valid .x)
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newdata[pw_deq ? r_count - 1 : r_count] = x;
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writeVReg(vr_data, newdata);
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endrule
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function Bool notFull;
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return r_count < fromInteger(valueOf(depth));
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endfunction
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function Bool notEmpty;
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return r_count != 0;
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endfunction
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function Maybe#(t) valid(Integer x, t a);
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if (fromInteger(x) < r_count)
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return tagged Valid a;
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else
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return tagged Invalid;
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endfunction
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Reg#(Bool) beforeEnq <- mkRevertingVirtualReg(True);
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Reg#(Bool) beforeDeq <- mkRevertingVirtualReg(True);
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Reg#(Bool) beforeClear <- mkRevertingVirtualReg(True);
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Bool beforeActions = beforeEnq && beforeDeq && beforeClear;
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interface FIFOF fifo;
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method Action enq(t x) if (notFull && beforeClear);
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w_enq.wset(x);
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beforeEnq <= False;
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endmethod
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method Action deq if (notEmpty && beforeClear);
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pw_deq.send;
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beforeDeq <= False;
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endmethod
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method t first if (beforeDeq && beforeClear && (r_count > 0)) = vr_data[0];
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method Action clear();
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pw_clear.send;
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beforeClear <= False;
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endmethod
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method Bool notFull() if (beforeActions) = notFull;
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method Bool notEmpty() if (beforeActions) = notEmpty;
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endinterface
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method vector() if (beforeActions) = zipWith(valid, genVector, readVReg(vr_data));
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endmodule
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endpackage

‎testing/bsc.contrib/Misc/Makefile‎

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# for "make clean" to work everywhere
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CONFDIR = $(realpath ../..)
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include $(CONFDIR)/clean.mk

‎testing/bsc.contrib/Misc/TestSched_VectorFIFOF.bsv‎

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import FIFOF ::*;
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import VectorFIFOF ::*;
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(* synthesize *)
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module mkVectorFIFOF_4_Bool(VectorFIFOF#(4,Bool));
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(* hide *)
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VectorFIFOF#(4,Bool) __i <- mkVectorFIFOF;
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return __i;
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endmodule

‎testing/bsc.contrib/Misc/TestSched_VectorFIFOF.bsv.bsc-sched-out.expected‎

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checking package dependencies
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compiling TestSched_VectorFIFOF.bsv
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code generation for mkVectorFIFOF_4_Bool starts
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=== schedule:
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parallel: [esposito: [fifo_enq -> [],
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fifo_deq -> [],
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fifo_first -> [],
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fifo_notFull -> [],
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fifo_notEmpty -> [],
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fifo_clear -> [],
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vector -> [],
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RL_rl_magic -> []]]
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order: [fifo_first,
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fifo_notFull,
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fifo_notEmpty,
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vector,
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fifo_enq,
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fifo_deq,
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fifo_clear,
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RL_rl_magic]
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-----
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=== resources:
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[(beforeClear.read, [(beforeClear.read, 1)]),
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(beforeClear.write, [(beforeClear.write 1'd1, 1)]),
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(beforeDeq.read, [(beforeDeq.read, 1)]),
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(beforeDeq.write, [(beforeDeq.write 1'd1, 1)]),
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(beforeEnq.read, [(beforeEnq.read, 1)]),
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(beforeEnq.write, [(beforeEnq.write 1'd1, 1)]),
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(pw_clear.whas, [(pw_clear.whas, 1)]),
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(pw_clear.wset, [(pw_clear.wset, 1)]),
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(pw_deq.whas, [(pw_deq.whas, 1)]),
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(pw_deq.wset, [(pw_deq.wset, 1)]),
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(r_count.read, [(r_count.read, 1)]),
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(r_count.write,
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[(if pw_clear_whas_OR_w_enq_whas_AND_NOT_pw_deq_wha_ETC___d9 then
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r_count.write IF_pw_clear_whas_THEN_0_ELSE_IF_w_enq_whas_AND_ETC___d14,
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1)]),
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(vr_data_0.read, [(vr_data_0.read, 1)]),
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(vr_data_0.write, [(vr_data_0.write IF_w_enq_whas_THEN_IF_IF_pw_deq_whas_THEN_r_co_ETC___d22, 1)]),
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(vr_data_1.read, [(vr_data_1.read, 1)]),
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(vr_data_1.write, [(vr_data_1.write IF_w_enq_whas_THEN_IF_IF_pw_deq_whas_THEN_r_co_ETC___d27, 1)]),
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(vr_data_2.read, [(vr_data_2.read, 1)]),
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(vr_data_2.write, [(vr_data_2.write IF_w_enq_whas_THEN_IF_IF_pw_deq_whas_THEN_r_co_ETC___d32, 1)]),
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(vr_data_3.read, [(vr_data_3.read, 1)]),
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(vr_data_3.write, [(vr_data_3.write IF_w_enq_whas_THEN_IF_IF_pw_deq_whas_THEN_r_co_ETC___d35, 1)]),
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(w_enq.wget, [(w_enq.wget, 1)]),
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(w_enq.whas, [(w_enq.whas, 1)]),
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(w_enq.wset, [(w_enq.wset fifo_enq_1, 1)])]
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-----
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=== vschedinfo:
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SchedInfo
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[RDY_fifo_clear CF [RDY_fifo_clear,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_fifo_deq CF [RDY_fifo_clear,
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RDY_fifo_deq,
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RDY_fifo_first,
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RDY_fifo_notEmpty,
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RDY_fifo_notFull,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_fifo_enq CF [RDY_fifo_clear,
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RDY_fifo_deq,
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RDY_fifo_enq,
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RDY_fifo_first,
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RDY_fifo_notEmpty,
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RDY_fifo_notFull,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_fifo_first CF [RDY_fifo_clear,
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RDY_fifo_first,
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RDY_fifo_notEmpty,
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RDY_fifo_notFull,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_fifo_notEmpty CF [RDY_fifo_clear,
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RDY_fifo_notEmpty,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_fifo_notFull CF [RDY_fifo_clear,
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RDY_fifo_notEmpty,
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RDY_fifo_notFull,
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RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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RDY_vector CF [RDY_vector,
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fifo_clear,
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fifo_deq,
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fifo_enq,
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fifo_first,
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fifo_notEmpty,
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fifo_notFull,
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vector],
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fifo_enq CF [fifo_deq, fifo_first],
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fifo_first CF [fifo_first, fifo_notEmpty, fifo_notFull, vector],
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fifo_notEmpty CF [fifo_notEmpty, vector],
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fifo_notFull CF [fifo_notEmpty, fifo_notFull, vector],
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vector CF vector,
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[fifo_deq, fifo_enq] SB fifo_clear,
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fifo_first SB [fifo_clear, fifo_deq],
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[fifo_notEmpty, fifo_notFull, vector] SB [fifo_clear, fifo_deq, fifo_enq],
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fifo_clear C fifo_clear,
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fifo_deq C fifo_deq,
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fifo_enq C fifo_enq]
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[]
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[]
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[]
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-----
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Schedule dump file created: mkVectorFIFOF_4_Bool.sched
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=== Generated schedule for mkVectorFIFOF_4_Bool ===
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Method schedule
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---------------
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Method: fifo_enq
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Ready signal: (r_count < 3'd4) && beforeClear.read
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Conflict-free: fifo_deq, fifo_first
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Sequenced before: fifo_clear
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Sequenced after: fifo_notFull, fifo_notEmpty, vector
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Conflicts: fifo_enq
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Method: fifo_deq
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Ready signal: (! (r_count == 3'd0)) && beforeClear.read
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Conflict-free: fifo_enq
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Sequenced before: fifo_clear
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Sequenced after: fifo_first, fifo_notFull, fifo_notEmpty, vector
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Conflicts: fifo_deq
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Method: fifo_first
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Ready signal: beforeDeq.read && beforeClear.read && (! (r_count == 3'd0))
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Conflict-free: fifo_enq, fifo_first, fifo_notFull, fifo_notEmpty, vector
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Sequenced before: fifo_deq, fifo_clear
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Method: fifo_notFull
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Ready signal: beforeEnq.read && beforeDeq.read && beforeClear.read
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Conflict-free: fifo_first, fifo_notFull, fifo_notEmpty, vector
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Sequenced before: fifo_enq, fifo_deq, fifo_clear
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Method: fifo_notEmpty
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Ready signal: beforeEnq.read && beforeDeq.read && beforeClear.read
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Conflict-free: fifo_first, fifo_notFull, fifo_notEmpty, vector
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Sequenced before: fifo_enq, fifo_deq, fifo_clear
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Method: fifo_clear
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Ready signal: True
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Sequenced after: fifo_enq,
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fifo_deq,
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fifo_first,
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fifo_notFull,
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fifo_notEmpty,
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vector
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Conflicts: fifo_clear
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Method: vector
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Ready signal: beforeEnq.read && beforeDeq.read && beforeClear.read
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Conflict-free: fifo_first, fifo_notFull, fifo_notEmpty, vector
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Sequenced before: fifo_enq, fifo_deq, fifo_clear
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Rule schedule
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-------------
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Rule: rl_magic
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Predicate: True
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Blocking rules: (none)
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Logical execution order: fifo_first,
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fifo_notFull,
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fifo_notEmpty,
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vector,
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fifo_enq,
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fifo_deq,
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fifo_clear,
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rl_magic
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====================================================
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Verilog file created: mkVectorFIFOF_4_Bool.v
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All packages are up to date.

‎testing/bsc.contrib/Misc/Test_VectorFIFOF.bsv‎

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import Cur_Cycle ::*;
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import FIFOF ::*;
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import VectorFIFOF ::*;
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(* synthesize *)
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module sysTest_VectorFIFOF();
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VectorFIFOF#(3,Bit#(4)) vf <- mkVectorFIFOF;
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Reg#(Bit#(4)) rg_send <- mkReg(0);
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rule do_enq (rg_send < 8);
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vf.fifo.enq(rg_send);
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rg_send <= rg_send + 1;
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$display("[%d] Contents: ", cur_cycle, fshow(vf.vector));
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$display("[%d] Enq %d", cur_cycle, rg_send);
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endrule
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Reg#(Bit#(4)) rg_recv <- mkReg(0);
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rule do_deq;
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vf.fifo.deq();
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$display("[%d] Deq %d", cur_cycle, vf.fifo.first);
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rg_recv <= rg_recv + 1;
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if (rg_recv == 7)
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$finish(0);
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endrule
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endmodule

‎testing/bsc.contrib/Misc/misc.exp‎

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# Include the boilerplate for bsc-contrib tests
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set here [file join [absolute $srcdir] $subdir]
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source $here/../contrib.tcl
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if { $contribtest } {
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add_contrib_dirs_to_path { Misc }
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# ---------------
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# VectorFIFOF
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# Check that the method scheduling relationships are as expected
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compile_verilog_schedule_pass TestSched_VectorFIFOF.bsv
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compare_file_filter_ids TestSched_VectorFIFOF.bsv.bsc-sched-out
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# Test that the module operates as a FIFO
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# and confirm that enq and deq occur in the same cycle
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# Note: The use of Cur_Cycle requires separate .ba elaboration
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test_c_veri_bsv_separately Test_VectorFIFOF
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# ---------------
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restore_path
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}

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