Renumber the foreign-proviso error tags to T0162/T0163

The typeclass-coherence PRs (#1035/#1037) claim T0159-T0161, and
whichever series merges second would collide.  Take the next free
numbers here proactively; the tags are otherwise arbitrary.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_019cqQdWKp7jr73GHQYnvhiq

Author: nanavati

src/comp/Error.hs

@@ -1945,15 +1945,15 @@ getErrorText (EForeignNotBit i t) =
   (Type 12, empty, hdr $$ text "Type:" <+> nest 2 (text t))
   where hdr = s2par ("Foreign function " ++ ishow i ++ " has a non-Bit argument or result.")
 getErrorText (EForeignCtxNotNumeric i p) =
-  (Type 160, empty, hdr $$ text "Proviso:" <+> nest 2 (text p))
+  (Type 163, empty, hdr $$ text "Proviso:" <+> nest 2 (text p))
   where hdr = s2par ("Foreign function " ++ ishow i ++ " has a proviso" ++
                      " that is not a numeric relationship." ++
                      " Only Add, Mul, Div, Log, Max, Min and NumEq" ++
                      " provisos are permitted on foreign functions:" ++
                      " they are checked at each application and then" ++
                      " erased.")
 getErrorText (EForeignWidthNotBare i t) =
-  (Type 159, empty, hdr $$ text "Width:" <+> nest 2 (text t))
+  (Type 162, empty, hdr $$ text "Width:" <+> nest 2 (text t))
   where hdr = s2par ("Foreign function " ++ ishow i ++ " has a bit width" ++
                      " that is not a bare type variable or a literal." ++
                      " Widths are passed to the module as instance" ++

testsuite/bsc.verilog/noinline/noinline.exp

@@ -77,13 +77,13 @@ compile_verilog_fail NoInline_Polymorphic.bsv T0111
 # A foreign function bound to a module must use a bare type variable or
 # a literal for every bit width (widths become instance parameters named
 # by the type variables; a type-function width has no name to pass)
-compile_verilog_fail BadForeignWidth.bs T0159
+compile_verilog_fail BadForeignWidth.bs T0162
 
 # Numeric provisos on foreign functions are permitted (checked at each
 # application, then erased); anything else is rejected
 compile_verilog_pass ForeignCtxGood.bs
 find_regexp sysForeignCtxGood.v {Dup #\(\.iw\(8\), \.ow\(16\)\)}
 compile_verilog_fail ForeignCtxViolated.bs T0031
-compile_verilog_fail ForeignCtxBad.bs T0160
+compile_verilog_fail ForeignCtxBad.bs T0163
 }