VCD visibility of mkPipelineFIFO and mkBypassFIFO #824
Description
I have been debugging a design that instantiates mkPipelineFIFOF and mkBypassFIFOF which are implemented in BSV (in SpecialFIFOs.bsv) and therefore do not have synthesis boundaries and are inlined into the design. When I want to view in the inputs and outputs in VCD, those signals are not visible. Has anyone faced this issue and have a suitable workaround?
I have several possible workarounds, but I think I'd like to propose that these modules just be implemented as Verilog primitives, like mkFIFOF etc. It's nice that it can be written in BSV, but I'm not sure that buys us anything: It adds complexity to the compile and simulation, and effort needs to be taken to make sure that the method scheduling relationships are correct (as opposed to specifying them by fiat in an import-BVI statement).
My current workaround is to replace these instantiations with mkFIFOF in my design, while debugging. Another option is to synthesis these modules for the specific sizes that I'm using -- separately-synthesized modules would have ports that I can view in the VCD dump. This can be made easy by using a typeclass, with a method (say, mkPipelineFIFOF_Synth), and instances can be populated for the various data widths that I need. (Similar to how the Bluetcl InstSynth script supports instance-specific synthesis.) Though, I guess, if we had synthesis for polymorphic modules, then I could just synthesize it once. But in the meantime, since we can import polymorphic primitives, that seems like the easiest thing.