Tic-Tac-Toe-On-FPGA/seven_seg_dec.sv.bak at master · BasRizk/Tic-Tac-Toe-On-FPGA · GitHub

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module seven_seg_dec(segments, num , enable);

input enable;
input[4:0] num;
output [6:0] segments;
reg [6:0] segments;

always@(num or enable)
begin

	if(enable = 1)
		case(num)
			0: segments <= ~7'b011_1111;		//  --0--
			1: segments <= ~7'b000_0110;		//  |    |
			2: segments <=  ~7'b1011011;     //  5    1
			3: segments   <=  ~7'b1001111;  	//  |    |
			4: segments <=  ~7'b1100110;    	//  --6--
			5: segments   <=  ~7'b1101101;   //  |    |
			6: segments <=  ~7'b1111101;    	//  4    2
			7: segments   <=  ~7'b0000111;  	//  |    |
			8: segments <=  ~7'b1111111;    	//  --3--
			9: segments   <=  ~7'b1101111;
			10: segments <= ~7'b0111001; // C
			11: segments <= ~7'b1110011; // P
			12: segments <= ~7'b1010000; // r
			default: segments  <=  7'bx;
	else
		segments <= 7'b1;

	endcase
end

endmodule