Open
Description
Like how currents are written in Verilog-A(MS) / VHDL-AMS - you can just do a += on the node.
But perhaps with a bit more safety, where parameters that can be added to need to be forward-declared as open (mutability is explicit). This needs to pass through arguments, eg self.pwr=VoltageSink(..., current_draw=ContributionRange([optional_initializer]), then later we could self.pwr.current_draw += (0, 0.5)*Amp.
Primary use case is for current draws, which in chips are often a sum of the current draw of their ports. The current (hah) solution is kind of nasty with dummy nodes.