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‎BrianHG_DDR3_CV_GFX_FMAX_Test_v15_350MHz_QR/AUDIO_IF.v‎

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// ============================================================================
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// Copyright (c) 2012 by Terasic Technologies Inc.
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// ============================================================================
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//
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// Permission:
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//
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// Terasic grants permission to use and modify this code for use
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// in synthesis for all Terasic Development Boards and Altera Development
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// Kits made by Terasic. Other use of this code, including the selling
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// ,duplication, or modification of any portion is strictly prohibited.
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//
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// Disclaimer:
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//
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// This VHDL/Verilog or C/C++ source code is intended as a design reference
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// which illustrates how these types of functions can be implemented.
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// It is the user's responsibility to verify their design for
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// consistency and functionality through the use of formal
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// verification methods. Terasic provides no warranty regarding the use
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// or functionality of this code.
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//
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// ============================================================================
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//
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// Terasic Technologies Inc
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// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
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//
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//
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//
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// web: http://www.terasic.com/
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// email: support@terasic.com
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//
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// ============================================================================
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/*
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Function:
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ADV7513 Video and Audio Control
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I2C Configuration Requirements:
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Master Mode
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I2S, 16-bits
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Clock:
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input Clock 1.536MHz (48K*Data_Width*Channel_Num)
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Revision:
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1.0, 10/06/2014, Init by Nick
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Compatibility:
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Quartus 14.0.2
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*/
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module AUDIO_IF(
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//
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reset_n,
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sclk,
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lrclk,
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i2s,
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clk
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);
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/*****************************************************************************
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* Constant Declarations *
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*****************************************************************************/
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/*****************************************************************************
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* Port Declarations *
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*****************************************************************************/
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//
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output sclk;
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output lrclk;
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input reset_n;
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output [3:0] i2s;
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input clk;
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parameter DATA_WIDTH = 16;
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parameter SIN_SAMPLE_DATA = 48;
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/*****************************************************************************
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* Internal wires and registers Declarations *
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*****************************************************************************/
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reg lrclk;
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reg [5:0] sclk_Count;
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reg [5:0] Simple_count;
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reg [15:0] Data_Bit;
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reg [6:0] Data_Count;
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reg [5:0] SIN_Cont;
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reg [3:0] i2s;
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/*****************************************************************************
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* Sequential logic *
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*****************************************************************************/
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assign sclk = clk;
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always@(negedge sclk or negedge reset_n)
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begin
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if(!reset_n)
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begin
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lrclk<=0;
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sclk_Count<=0;
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end
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else if(sclk_Count>=DATA_WIDTH-1)
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begin
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sclk_Count <= 0;
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lrclk <= ~lrclk;
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end
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else
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sclk_Count <= sclk_Count + 1;
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end
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always@(negedge sclk or negedge reset_n)
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begin
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if(!reset_n)
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begin
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Data_Count <= 0;
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end
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else
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begin
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if(Data_Count >= DATA_WIDTH-1)
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begin
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Data_Count <= 0;
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end
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else
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Data_Count <= Data_Count +1;
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end
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end
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always@(negedge sclk or negedge reset_n)
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begin
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if(!reset_n)
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begin
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i2s <= 0;
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end
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else
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begin
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i2s[0] <= Data_Bit[~Data_Count];
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i2s[1] <= Data_Bit[~Data_Count];
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i2s[2] <= Data_Bit[~Data_Count];
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i2s[3] <= Data_Bit[~Data_Count];
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end
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end
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always@(negedge lrclk or negedge reset_n)
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begin
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if(!reset_n)
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SIN_Cont <= 0;
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else
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begin
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if(SIN_Cont < SIN_SAMPLE_DATA-1 )
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SIN_Cont <= SIN_Cont+1;
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else
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SIN_Cont <= 0;
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end
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end
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/*****************************************************************************
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* Combinational logic *
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*****************************************************************************/
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always@(SIN_Cont)
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begin
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case(SIN_Cont)
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0 : Data_Bit <= 0 ;
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1 : Data_Bit <= 4276 ;
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2 : Data_Bit <= 8480 ;
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3 : Data_Bit <= 12539 ;
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4 : Data_Bit <= 16383 ;
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5 : Data_Bit <= 19947 ;
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6 : Data_Bit <= 23169 ;
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7 : Data_Bit <= 25995 ;
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8 : Data_Bit <= 28377 ;
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9 : Data_Bit <= 30272 ;
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10 : Data_Bit <= 31650 ;
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11 : Data_Bit <= 32486 ;
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12 : Data_Bit <= 32767 ;
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13 : Data_Bit <= 32486 ;
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14 : Data_Bit <= 31650 ;
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15 : Data_Bit <= 30272 ;
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16 : Data_Bit <= 28377 ;
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17 : Data_Bit <= 25995 ;
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18 : Data_Bit <= 23169 ;
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19 : Data_Bit <= 19947 ;
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20 : Data_Bit <= 16383 ;
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21 : Data_Bit <= 12539 ;
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22 : Data_Bit <= 8480 ;
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23 : Data_Bit <= 4276 ;
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24 : Data_Bit <= 0 ;
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25 : Data_Bit <= 61259 ;
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26 : Data_Bit <= 57056 ;
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27 : Data_Bit <= 52997 ;
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28 : Data_Bit <= 49153 ;
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29 : Data_Bit <= 45589 ;
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30 : Data_Bit <= 42366 ;
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31 : Data_Bit <= 39540 ;
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32 : Data_Bit <= 37159 ;
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33 : Data_Bit <= 35263 ;
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34 : Data_Bit <= 33885 ;
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35 : Data_Bit <= 33049 ;
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36 : Data_Bit <= 32768 ;
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37 : Data_Bit <= 33049 ;
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38 : Data_Bit <= 33885 ;
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39 : Data_Bit <= 35263 ;
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40 : Data_Bit <= 37159 ;
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41 : Data_Bit <= 39540 ;
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42 : Data_Bit <= 42366 ;
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43 : Data_Bit <= 45589 ;
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44 : Data_Bit <= 49152 ;
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45 : Data_Bit <= 52997 ;
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46 : Data_Bit <= 57056 ;
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47 : Data_Bit <= 61259 ;
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default :
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Data_Bit <= 0 ;
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endcase
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end
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endmodule
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‎BrianHG_DDR3_CV_GFX_FMAX_Test_v15_350MHz_QR/BrianHG_DDR3_CV.sdc‎

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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -period "50.0 MHz" [get_ports CLK_IN_50]
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create_clock -period "50.0 MHz" [get_ports CLK_IN_50_vid]
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create_clock -period "1.0 MHz" [get_nets {I2C_HDMI_Config:u_I2C_HDMI_Config|mI2C_CTRL_CLK}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#Specify the required tSU
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set tSU 0.500
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#Specify the required tH
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set tH 2.000
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#Specify the required tCO 9 96 = 7.5
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#Use -7.5 for -6 Altera FPGA
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#Use -8.0 for -7 Altera FPGA
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#Use -8.5 for -8 Altera FPGA
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set tCO -7.500
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#Specify the required tCOm
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set tCOm -3.800
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##**************************************************************
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## Set Input Delay
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##**************************************************************
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[2]*}] -max -add_delay $tSU [get_ports {DDR3_DQ*[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[2]*}] -min -add_delay $tH [get_ports {DDR3_DQ*[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[2]*}] -clock_fall -max -add_delay $tSU [get_ports {DDR3_DQ*[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[2]*}] -clock_fall -min -add_delay $tH [get_ports {DDR3_DQ*[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tSU [get_ports {GPIO0_D[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tH [get_ports {GPIO0_D[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tSU [get_ports {KEY[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tH [get_ports {KEY[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tSU [get_ports {SW[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tH [get_ports {SW[*]}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tSU [get_ports {HDMI_I2C_SDA}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tH [get_ports {HDMI_I2C_SDA}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tSU [get_ports {HDMI_TX_INT}]
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set_input_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tH [get_ports {HDMI_TX_INT}]
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##**************************************************************
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## Set Output Delay
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##**************************************************************
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[0]*}] -max $tCO [get_ports {DDR3*}] -add_delay
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[0]*}] -max $tCO -clock_fall [get_ports {DDR3*}] -add_delay
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[0]*}] -min $tCOm [get_ports {DDR3*}] -add_delay
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[0]*}] -min $tCOm -clock_fall [get_ports {DDR3*}] -add_delay
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tCO [get_ports {GPIO0_D[*]}]
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tCOm [get_ports {GPIO0_D[*]}]
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -max $tCO [get_ports {LED[*]}]
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set_output_delay -clock [get_clocks {*DDR3_PLL5*counter[4]*}] -min $tCOm [get_ports {LED[*]}]
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set_output_delay -clock CLK_IN_50_vid -max $tCO [get_ports {HDMI*}]
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set_output_delay -clock CLK_IN_50_vid -min $tCOm [get_ports {HDMI*}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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# Separate VGA output video pixel clock from the main system clock and CLK_In 50Mhz clock.
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set_false_path -from [get_clocks {u_vpg|u_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {CLK_IN_50_vid}]
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set_false_path -from [get_clocks {u_vpg|u_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {*DDR3_PLL5*counter[4]*}]
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set_false_path -from [get_clocks {u_vpg|u_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {*DDR3_PLL5*counter[3]*}]
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set_false_path -from [get_clocks {*DDR3_PLL5*counter[4]*}] -to [get_clocks {u_vpg|u_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set_false_path -from [get_clocks {*DDR3_PLL5*counter[3]*}] -to [get_clocks {u_vpg|u_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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# Separate the fake generated I2C clock output from the CLK_IN 50 MHz source.
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set_false_path -from [get_clocks {CLK_IN_50}] -to [get_clocks {u_I2C_HDMI_Config|mI2C_CTRL_CLK|q}]
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set_false_path -from [get_clocks {*DDR3_PLL5*counter[4]*}] -to [get_clocks {u_I2C_HDMI_Config|mI2C_CTRL_CLK|q}]
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# Optional: Separate the reset and low frequency inputs on the CLK_IN 50Mhz from the core.
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set_false_path -from [get_clocks {*DDR3_PLL5*counter[4]*}] -to [get_clocks {CLK_IN_50}]
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set_false_path -from [get_clocks {CLK_IN_50}] -to [get_clocks {*DDR3_PLL5*counter[4]*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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# Set Load
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#**************************************************************

‎BrianHG_DDR3_CV_GFX_FMAX_Test_v15_350MHz_QR/BrianHG_DDR3_CV_top.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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# Date created = 22:09:02 March 10, 2021
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "20.1"
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DATE = "22:09:02 March 10, 2021"
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# Revisions
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PROJECT_REVISION = "BrianHG_DDR3_CV_top"

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