We could add JLCPCB Design Rules and possibly pre configured stack ups?

[CDFER]

Design rules already exist here but maybe they could be improved especially around instructions:
https://github.com/labtroll/KiCad-DesignRules/blob/main/JLCPCB/JLCPCB.kicad_dru

Pre configured stack ups as pcb files or whole project folders (Current/impedance rated trace width net classes...?)