Add RVC HINT/RES/NSE encs & rework disassembly

Add explicit HINT, Reserved, and NSE compressed instruction
encodings from the spec.
This allows Templates to more easily specify these special encodings
and enables more accurate disassembly.
Note that some encodings overlap.

Add new instruction disassembly pretty printer functions
for special cases where the operands are uninteresting or ambiguous.

Rework the disassembly to account for overlapping encodings.
Use XLEN, when available, and carful ordering to distinguish
overlapping encodings from each other.
Present both encodings when encodings overlap and XLEN is not available.

Integrate new disassembly so that XLEN will be passed through when known
(currently only for RVFI V2 packets).

Minor errors may remain.
Caution only goes so far when there are so many fiddly changes required.

Author: elliotb-lowrisc

Diff for: src/QuickCheckVEngine/RVFI_DII/RVFI.hs

@@ -420,7 +420,7 @@ instance Show RVFI_Packet where
         (rvfi_insn tok)
         (privString (rvfi_mode tok))
         (xlenString (rvfi_ixl tok))
-        (rv_pretty (MkInstruction (toInteger (rvfi_insn tok)))) -- Inst
+        (rv_pretty (MkInstruction (toInteger (rvfi_insn tok))) (rvfi_ixl tok)) -- Inst
 
 -- | Return 'True' for halt 'RVFI_Packet's
 rvfiIsHalt :: RVFI_Packet -> Bool

Diff for: src/RISCV/Helpers.hs

@@ -85,6 +85,7 @@ module RISCV.Helpers (
 , prettyCSS
 , prettyCSS_F
 , prettyCIW
+, prettyCIW_reg
 , prettyCL
 , prettyCL_F
 , prettyCS
@@ -94,6 +95,9 @@ module RISCV.Helpers (
 , prettyCB_sig
 , prettyCB_reg
 , prettyCJ
+, prettyIgnr1
+, prettyIgnr2
+, prettyIgnr3
 -- * Others
 , reg
 , int
@@ -406,6 +410,9 @@ prettyCSS_F instr imm rs2 =
 -- | CIW-type 'Wide-Immediate' compressed instruction pretty printer
 prettyCIW instr imm rd' =
   concat [instr, " ", reg' rd', ", ", int imm]
+-- | CIW-type (register-only variant)
+prettyCIW_reg instr rd' =
+  concat [instr, " ", reg' rd']
 
 -- | CL-type 'Load' compressed instruction pretty printer
 prettyCL instr imm rd' rs1' =
@@ -439,6 +446,15 @@ prettyCB_reg instr rs1' =
 prettyCJ instr imm =
   concat [instr, " ", int $ toSigned 12 imm]
 
+-- | Operand-swallowing instruction pretty printers.
+-- | Useful for special cases, such as reserved or overlapping encodings.
+prettyIgnr1 :: String -> Integer -> String
+prettyIgnr1 instr _     = instr
+prettyIgnr2 :: String -> Integer -> Integer -> String
+prettyIgnr2 instr _ _   = instr
+prettyIgnr3 :: String -> Integer -> Integer -> Integer-> String
+prettyIgnr3 instr _ _ _ = instr
+
 type ExtractedRegs = ( Bool -- ^ is_bypass
                      , Maybe Integer -- ^ rs2
                      , Maybe Integer -- ^ rs1

Diff for: src/RISCV/InstInspect.hs

@@ -74,8 +74,8 @@ import RISCV.Helpers
 import Text.Printf
 
 -- | RISC-V instruction pretty printer
-rv_pretty :: Instruction -> String
-rv_pretty instr = case decode 32 instr instList of
+rv_pretty :: Instruction -> Maybe XLen-> String
+rv_pretty instr ixl = case decode 32 instr instList of
   Nothing -> "Unknown instruction"
   Just i -> i
   where instList =    rv32_i_disass ++ rv64_i_disass
@@ -86,10 +86,10 @@ rv_pretty instr = case decode 32 instr instList of
                    ++ rv32_zicsr_disass
                    ++ rv32_zifencei_disass
                    ++ rv32_xcheri_disass
-                   ++ rv_c_disass
+                   ++ rv_c_disass ixl
 
 instance Show Instruction where
-  show i@(MkInstruction v) = printf ".4byte 0x%08x # %s" v (rv_pretty i)
+  show i@(MkInstruction v) = printf ".4byte 0x%08x # %s" v (rv_pretty i Nothing)
 
 rv_extract :: Instruction -> ExtractedRegs
 rv_extract instr = case decode 32 instr extractList of