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Add RISCV bitmanip extension
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‎QCVEngine.cabal

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@@ -17,6 +17,7 @@ executable QCVEngine
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RISCV.RV32_A,
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RISCV.RV32_F,
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RISCV.RV32_D,
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RISCV.RV32_B,
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RISCV.RV32_Zifencei,
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RISCV.RV32_Zicsr,
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RISCV.RV32_Xcheri,
@@ -25,6 +26,7 @@ executable QCVEngine
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RISCV.RV64_A,
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RISCV.RV64_F,
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RISCV.RV64_D,
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RISCV.RV64_B,
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RISCV.RV_C,
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RISCV.RV_CSRs,
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RISCV.HPMEvents,

‎src/RISCV.hs

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@@ -50,6 +50,7 @@ module RISCV (
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, module RISCV.RV32_A
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, module RISCV.RV32_F
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, module RISCV.RV32_D
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, module RISCV.RV32_B
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, module RISCV.RV32_Zicsr
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, module RISCV.RV32_Zifencei
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, module RISCV.RV32_Xcheri
@@ -58,6 +59,7 @@ module RISCV (
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, module RISCV.RV64_A
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, module RISCV.RV64_F
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, module RISCV.RV64_D
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, module RISCV.RV64_B
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, module RISCV.RV_C
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, module RISCV.RV_CSRs
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, module RISCV.HPMEvents
@@ -74,6 +76,7 @@ import RISCV.RV32_M
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import RISCV.RV32_A
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import RISCV.RV32_F
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import RISCV.RV32_D
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import RISCV.RV32_B hiding (rori, bclri, bexti, binvi, bseti)
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import RISCV.RV32_Zicsr
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import RISCV.RV32_Zifencei
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import RISCV.RV32_Xcheri
@@ -82,6 +85,7 @@ import RISCV.RV64_M
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import RISCV.RV64_A
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import RISCV.RV64_F
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import RISCV.RV64_D
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import RISCV.RV64_B
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import RISCV.RV_C
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import RISCV.RV_CSRs
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import RISCV.HPMEvents

‎src/RISCV/RV32_B.hs

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@@ -0,0 +1,220 @@
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--
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-- SPDX-License-Identifier: BSD-2-Clause
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--
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-- Copyright (c) 2019-2020 Alexandre Joannou
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-- Copyright (c) 2020 Peter Rugg
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-- Copyright (c) 2025 SCI Semiconductor
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-- All rights reserved.
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--
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-- This software was developed by SRI International and the University of
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-- Cambridge Computer Laboratory (Department of Computer Science and
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-- Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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-- DARPA SSITH research programme.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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-- SUCH DAMAGE.
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--
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{-|
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Module : RISCV.RV32_B
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Description : RISC-V RV32 bit manipulation extensions
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The 'RISCV.RV32_B' module provides the description of the RISC-V RV32
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Bit-Manipulation extension
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-}
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module RISCV.RV32_B (
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-- * RV32 bitmanip, instruction definitions
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sh1add
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, sh2add
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, sh3add
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, andn
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, orn
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, xnor
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, clz
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, ctz
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, cpop
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, max
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, maxu
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, min
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, minu
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, sext_b
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, sext_h
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, zext_h
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, rol
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, ror
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, rori
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, orc_b
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, rev8
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, clmul
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, clmulh
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, clmulr
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, bclr
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, bclri
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, bext
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, bexti
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, binv
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, binvi
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, bset
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, bseti
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, -- * RV32 bitmanip, others
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rv32_b_disass
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) where
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import RISCV.Helpers (prettyR, prettyI, prettyR_nors2)
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import InstrCodec (DecodeBranch, (-->), encode, Instruction)
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import Prelude hiding (min, max)
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-- Zba
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sh1add_raw = "0010000 rs2[4:0] rs1[4:0] 010 rd[4:0] 0110011"
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sh1add rd rs1 rs2 = encode sh1add_raw rs2 rs1 rd
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sh2add_raw = "0010000 rs2[4:0] rs1[4:0] 100 rd[4:0] 0110011"
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sh2add rd rs1 rs2 = encode sh2add_raw rs2 rs1 rd
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sh3add_raw = "0010000 rs2[4:0] rs1[4:0] 110 rd[4:0] 0110011"
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sh3add rd rs1 rs2 = encode sh3add_raw rs2 rs1 rd
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-- Zbb
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andn_raw = "0100000 rs2[4:0] rs1[4:0] 111 rd[4:0] 0110011"
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andn rd rs1 rs2 = encode andn_raw rs2 rs1 rd
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orn_raw = "0100000 rs2[4:0] rs1[4:0] 110 rd[4:0] 0110011"
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orn rd rs1 rs2 = encode orn_raw rs2 rs1 rd
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xnor_raw = "0100000 rs2[4:0] rs1[4:0] 100 rd[4:0] 0110011"
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xnor rd rs1 rs2 = encode xnor_raw rs2 rs1 rd
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clz_raw = "0110000 00000 rs1[4:0] 001 rd[4:0] 0010011"
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clz rd rs1 = encode clz_raw rs1 rd
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ctz_raw = "0110000 00001 rs1[4:0] 001 rd[4:0] 0010011"
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ctz rd rs1 = encode ctz_raw rs1 rd
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cpop_raw = "0110000 00010 rs1[4:0] 001 rd[4:0] 0010011"
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cpop rd rs1 = encode cpop_raw rs1 rd
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max_raw = "0000101 rs2[4:0] rs1[4:0] 110 rd[4:0] 0110011"
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max rd rs1 rs2 = encode max_raw rs2 rs1 rd
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maxu_raw = "0000101 rs2[4:0] rs1[4:0] 111 rd[4:0] 0110011"
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maxu rd rs1 rs2 = encode maxu_raw rs2 rs1 rd
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min_raw = "0000101 rs2[4:0] rs1[4:0] 100 rd[4:0] 0110011"
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min rd rs1 rs2 = encode min_raw rs2 rs1 rd
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minu_raw = "0000101 rs2[4:0] rs1[4:0] 101 rd[4:0] 0110011"
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minu rd rs1 rs2 = encode minu_raw rs2 rs1 rd
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sext_b_raw = "0110000 00100 rs1[4:0] 001 rd[4:0] 0010011"
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sext_b rd rs1 = encode sext_b_raw rs1 rd
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sext_h_raw = "0110000 00101 rs1[4:0] 001 rd[4:0] 0010011"
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sext_h rd rs1 = encode sext_h_raw rs1 rd
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zext_h_raw = "0000100 00000 rs1[4:0] 100 rd[4:0] 0110011"
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zext_h rd rs1 = encode zext_h_raw rs1 rd
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-- Bitwise rotation
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rol_raw = "0110000 rs2[4:0] rs1[4:0] 001 rd[4:0] 0110011"
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rol rd rs1 rs2 = encode rol_raw rs2 rs1 rd
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ror_raw = "0110000 rs2[4:0] rs1[4:0] 101 rd[4:0] 0110011"
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ror rd rs1 rs2 = encode ror_raw rs2 rs1 rd
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-- The RV64 and RV32 encodings differ by the width of the shamt field, with
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-- RV32 specifying that shamt[5] is 0. Import qualified if needed.
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rori_raw = "0110000 shamt[4:0] rs1[4:0] 101 rd[4:0] 0010011"
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rori rd rs1 shamt = encode rori_raw shamt rs1 rd
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orc_b_raw = "0010100 00111 rs1[4:0] 101 rd[4:0] 0010011"
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orc_b rd rs1 = encode orc_b_raw rs1 rd
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rev8_raw = "0110100 11000 rs1[4:0] 101 rd[4:0] 0010011"
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rev8 rd rs1 = encode rev8_raw rs1 rd
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-- Zbc
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clmul_raw = "0000101 rs2[4:0] rs1[4:0] 001 rd[4:0] 0110011"
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clmul rd rs1 rs2 = encode clmul_raw rs2 rs1 rd
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clmulh_raw = "0000101 rs2[4:0] rs1[4:0] 011 rd[4:0] 0110011"
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clmulh rd rs1 rs2 = encode clmulh_raw rs2 rs1 rd
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clmulr_raw = "0000101 rs2[4:0] rs1[4:0] 010 rd[4:0] 0110011"
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clmulr rd rs1 rs2 = encode clmulr_raw rs2 rs1 rd
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-- Zbs
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bclr_raw = "0100100 rs2[4:0] rs1[4:0] 001 rd[4:0] 0110011"
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bclr rd rs1 rs2 = encode bclr_raw rs2 rs1 rd
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-- The RV64 and RV32 encodings differ by the width of the shamt field, with
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-- RV32 specifying that shamt[5] is 0. Import qualified if needed.
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bclri_raw = "0100100 shamt[4:0] rs1[4:0] 001 rd[4:0] 0010011"
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bclri rd rs1 shamt = encode bclri_raw shamt rs1 rd
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bext_raw = "0100100 rs2[4:0] rs1[4:0] 101 rd[4:0] 0110011"
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bext rd rs1 rs2 = encode bext_raw rs2 rs1 rd
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-- The RV64 and RV32 encodings differ by the width of the shamt field, with
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-- RV32 specifying that shamt[5] is 0. Import qualified if needed.
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bexti_raw = "0100100 shamt[4:0] rs1[4:0] 101 rd[4:0] 0010011"
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bexti rd rs1 shamt = encode bexti_raw shamt rs1 rd
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binv_raw = "0110100 rs2[4:0] rs1[4:0] 001 rd[4:0] 0110011"
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binv rd rs1 rs2 = encode binv_raw rs2 rs1 rd
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-- The RV64 and RV32 encodings differ by the width of the shamt field, with
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-- RV32 specifying that shamt[5] is 0. Import qualified if needed.
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binvi_raw = "0110100 shamt[4:0] rs1[4:0] 001 rd[4:0] 0010011"
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binvi rd rs1 shamt = encode binvi_raw shamt rs1 rd
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bset_raw = "0010100 rs2[4:0] rs1[4:0] 001 rd[4:0] 0110011"
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bset rd rs1 rs2 = encode bset_raw rs2 rs1 rd
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-- The RV64 and RV32 encodings differ by the width of the shamt field, with
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-- RV32 specifying that shamt[5] is 0. Import qualified if needed.
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bseti_raw = "0010100 shamt[4:0] rs1[4:0] 001 rd[4:0] 0010011"
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bseti rd rs1 shamt = encode bseti_raw shamt rs1 rd
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rv32_b_disass :: [DecodeBranch String]
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rv32_b_disass = [ sh1add_raw --> prettyR "sh1add"
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, sh2add_raw --> prettyR "sh2add"
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, sh3add_raw --> prettyR "sh3add"
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, andn_raw --> prettyR "andn"
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, orn_raw --> prettyR "orn"
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, xnor_raw --> prettyR "xnor"
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, clz_raw --> prettyR_nors2 "clz"
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, ctz_raw --> prettyR_nors2 "ctz"
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, cpop_raw --> prettyR_nors2 "cpop"
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, max_raw --> prettyR "max"
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, maxu_raw --> prettyR "maxu"
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, min_raw --> prettyR "min"
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, minu_raw --> prettyR "minu"
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, sext_b_raw --> prettyR_nors2 "sext.b"
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, sext_h_raw --> prettyR_nors2 "sext.h"
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, zext_h_raw --> prettyR_nors2 "zext.h"
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, rol_raw --> prettyR "rol"
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, ror_raw --> prettyR "ror"
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, rori_raw --> prettyI "rori"
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, orc_b_raw --> prettyR_nors2 "orc.b"
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, rev8_raw --> prettyR_nors2 "rev8.b"
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, clmul_raw --> prettyR "clmul"
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, clmulh_raw --> prettyR "clmulh"
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, clmulr_raw --> prettyR "clmulr"
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, bclr_raw --> prettyR "bclr"
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, bclri_raw --> prettyI "bclri"
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, bext_raw --> prettyR "bext"
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, bexti_raw --> prettyI "bexti"
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, binv_raw --> prettyR "binv"
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, binvi_raw --> prettyI "binvi"
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, bset_raw --> prettyR "bset"
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, bseti_raw --> prettyI "bseti"
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]

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