Add more prose on direct memory-offset MOVs.

Recommend deprecating these instructions in capability mode and not
extending the immediate memory offsets to support capability
immediates.

Author: bsdjhb

chap-cheri-x86-64.tex

@@ -274,6 +274,7 @@ \subsubsection{Deprecated Instructions in Capability Mode}
   \item \insnnoref{LSS}
   \item \insnnoref{LAR}
   \item \insnnoref{LSL}
+  \item Direct memory-offset \insnnoref{MOV}
 \end{itemize}
 
 \subsection{Using Capabilities with Memory Address Operands}
@@ -373,6 +374,18 @@ \subsubsection{Absolute Addresses}
 register.  These operands are always evaluated as offsets relative to
 \DDC{} including in capability mode.
 
+\subsubsection{Direct Memory-Offset MOVs}
+
+The direct memory-offset \insnnoref{MOV} instructions store the
+absolute address of a memory operand as an immediate operand.
+Extending these instructions to support capability immediates would
+require padding nops to align the capability immediate as well as text
+relocations (even for position-dependent code).  However, we do not
+anticipate wide use of these instructions so instead choose to
+restrict memory offsets to integers.  Attempting to use these
+instructions with capability-aware addressing would be reserved and
+raise a UD\# exception.
+
 \subsubsection{Addresses Relative to CFS and CGS}
 
 Capability-aware addressing must also permit addresses defined as
@@ -488,7 +501,7 @@ \subsubsection{Extending Existing Instructions to Support Capability Operands}
     Note that these instructions would only permit a general-purpose
     register as the source (\texttt{89}) or destination (\texttt{8B}).
 
-    The \texttt{A1} and \texttt{A2} opcodes would be extended to use
+    The \texttt{A1} and \texttt{A3} opcodes would be extended to use
     \CAX{} as the implicit operand when used with the capability
     operand prefix.
 
@@ -1399,3 +1412,11 @@ \subsection{Far Branches and Capabilities}
 sense to deprecate far branches other than \insnnoref{IRET} completely
 in capability mode causing the instructions to raise an illegal
 instruction fault.
+
+\subsection{Direct Memory-Offset MOVs}
+
+These four \insnnoref{MOV} instructions store the address of their
+memory operand inline as an immediate.  These instructions could be
+extended to support capability immediates for the memory offset.  In
+that case, the opcodes would be retained in capability mode rather
+than deprecated.