CHERI riscv: PTE load-side caveats for non-LCG behaviors

Author: nwf

target/riscv/cpu_helper.c

@@ -706,8 +706,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                 *prot |= PAGE_WRITE;
             }
 #if defined(TARGET_CHERI) && !defined(TARGET_RISCV32)
-            if ((pte & PTE_LC) == 0)
-                *prot |= PAGE_LC_CLEAR;
+            if ((pte & PTE_LC) == 0) {
+                if ((pte & PTE_LCM) == 0) {
+                    *prot |= PAGE_LC_CLEAR;
+                } else {
+                    *prot |= PAGE_LC_TRAP;
+                }
+            }
 #endif
             return TRANSLATE_SUCCESS;
         }