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Prepare xccsr for s-mode bits
Split uccsr out to its own thing; remove mccsr and have accesses alias sccsr.
1 parent 379da8f commit 08dabbc

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3 files changed

+7
-14
lines changed

3 files changed

+7
-14
lines changed

src/cheri_regs.sail

-2
Original file line numberDiff line numberDiff line change
@@ -207,8 +207,6 @@ function ext_init_regs () = {
207207
x31 = null_cap;
208208

209209
misa->X() = 0b1;
210-
mccsr->d() = 0b1;
211-
mccsr->e() = 0b1;
212210
sccsr->d() = 0b1;
213211
sccsr->e() = 0b1;
214212
uccsr->d() = 0b1;

src/cheri_step_ext.sail

-2
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,6 @@
6565
val ext_init : unit -> unit effect {wreg}
6666
function ext_init () = {
6767
misa->X() = 0b1;
68-
mccsr->d() = 0b1;
69-
mccsr->e() = 0b1;
7068
sccsr->d() = 0b1;
7169
sccsr->e() = 0b1;
7270
uccsr->d() = 0b1;

src/cheri_sys_regs.sail

+7-10
Original file line numberDiff line numberDiff line change
@@ -69,18 +69,15 @@ bitfield ccsr : xlenbits = {
6969
e : 0 /* enable */
7070
}
7171

72-
register mccsr : ccsr
73-
register sccsr : ccsr
72+
register sccsr : ccsr /* mccsr aliases sccsr */
7473
register uccsr : ccsr
7574

7675
/* access to CCSRs */
7776

78-
// for now, use a single privilege-independent legalizer
79-
function legalize_ccsr(c : ccsr, v : xlenbits) -> ccsr = {
77+
function legalize_ccsr(csrp : Privilege, c : ccsr, v : xlenbits) -> ccsr = {
8078
// write only the defined bits, leaving the other bits untouched
81-
// Technically, WPRI does not need a legalizer, since software is
82-
// assumed to legalize; so we could remove this function.
8379
let v = Mk_ccsr(v);
80+
8481
/* For now these bits are not really supported so hardwired to true */
8582
let c = update_d(c, 0b1);
8683
let c = update_e(c, 0b1);
@@ -94,11 +91,11 @@ function legalize_ccsr(c : ccsr, v : xlenbits) -> ccsr = {
9491

9592
function clause ext_read_CSR (0x8C0) = Some(uccsr.bits())
9693
function clause ext_read_CSR (0x9C0) = Some(sccsr.bits())
97-
function clause ext_read_CSR (0xBC0) = Some(mccsr.bits())
94+
function clause ext_read_CSR (0xBC0) = Some(sccsr.bits())
9895

99-
function clause ext_write_CSR (0x8C0, value) = { uccsr = legalize_ccsr(uccsr, value); Some(uccsr.bits()) }
100-
function clause ext_write_CSR (0x9C0, value) = { sccsr = legalize_ccsr(sccsr, value); Some(sccsr.bits()) }
101-
function clause ext_write_CSR (0xBC0, value) = { mccsr = legalize_ccsr(mccsr, value); Some(mccsr.bits()) }
96+
function clause ext_write_CSR (0x8C0, value) = { uccsr = legalize_ccsr(User, uccsr, value); Some(uccsr.bits()) }
97+
function clause ext_write_CSR (0x9C0, value) = { sccsr = legalize_ccsr(Supervisor, sccsr, value); Some(sccsr.bits()) }
98+
function clause ext_write_CSR (0xBC0, value) = { sccsr = legalize_ccsr(Machine, sccsr, value); Some(sccsr.bits()) }
10299

103100
function clause ext_is_CSR_defined (0x8C0, p) = haveUsrMode() // uccsr
104101
function clause ext_is_CSR_defined (0x9C0, p) = haveSupMode() & (p == Machine | p == Supervisor) // sccsr

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