Prepare xccsr for s-mode bits

Split uccsr out to its own thing; remove mccsr and have accesses alias sccsr.

Author: nwf-msr

src/cheri_regs.sail

@@ -145,8 +145,6 @@ function ext_init_regs () = {
   x31 = null_cap;
 
   misa->X() = 0b1;
-  mccsr->d() = 0b1;
-  mccsr->e() = 0b1;
   sccsr->d() = 0b1;
   sccsr->e() = 0b1;
   uccsr->d() = 0b1;

src/cheri_step_ext.sail

@@ -3,8 +3,6 @@
 val ext_init : unit -> unit effect {wreg}
 function ext_init () = {
   misa->X() = 0b1;
-  mccsr->d() = 0b1;
-  mccsr->e() = 0b1;
   sccsr->d() = 0b1;
   sccsr->e() = 0b1;
   uccsr->d() = 0b1;

src/cheri_sys_regs.sail

@@ -7,18 +7,24 @@ bitfield ccsr : xlenbits = {
   e       :  0       /* enable */
 }
 
-register mccsr : ccsr
-register sccsr : ccsr
+register sccsr : ccsr /* mccsr aliases sccsr */
 register uccsr : ccsr
 
 /* access to CCSRs */
 
-// for now, use a single privilege-independent legalizer
-function legalize_ccsr(c : ccsr, v : xlenbits) -> ccsr = {
+function legalize_uccsr(c : ccsr, v : xlenbits) -> ccsr = {
+  // There are no defined bits in UCCSR, so ignore v
+
+  /* For now these bits are not really supported so hardwired to true */
+  let c = update_d(c, 0b1);
+  let c = update_e(c, 0b1);
+  c
+}
+
+function legalize_sccsr(c : ccsr, v : xlenbits) -> ccsr = {
   // write only the defined bits, leaving the other bits untouched
-  // Technically, WPRI does not need a legalizer, since software is
-  // assumed to legalize; so we could remove this function.
   let v = Mk_ccsr(v);
+
   /* For now these bits are not really supported so hardwired to true */
   let c = update_d(c, 0b1);
   let c = update_e(c, 0b1);
@@ -32,11 +38,11 @@ function legalize_ccsr(c : ccsr, v : xlenbits) -> ccsr = {
 
 function clause ext_read_CSR (0x8C0) = Some(uccsr.bits())
 function clause ext_read_CSR (0x9C0) = Some(sccsr.bits())
-function clause ext_read_CSR (0xBC0) = Some(mccsr.bits())
+function clause ext_read_CSR (0xBC0) = Some(sccsr.bits())
 
-function clause ext_write_CSR (0x8C0, value) = { uccsr = legalize_ccsr(uccsr, value); Some(uccsr.bits()) }
-function clause ext_write_CSR (0x9C0, value) = { sccsr = legalize_ccsr(sccsr, value); Some(sccsr.bits()) }
-function clause ext_write_CSR (0xBC0, value) = { mccsr = legalize_ccsr(mccsr, value); Some(mccsr.bits()) }
+function clause ext_write_CSR (0x8C0, value) = { uccsr = legalize_uccsr(uccsr, value); Some(uccsr.bits()) }
+function clause ext_write_CSR (0x9C0, value) = { sccsr = legalize_sccsr(sccsr, value); Some(sccsr.bits()) }
+function clause ext_write_CSR (0xBC0, value) = { sccsr = legalize_sccsr(sccsr, value); Some(sccsr.bits()) }
 
 function clause ext_is_CSR_defined (0x8C0, p) = haveUsrMode()  // uccsr
 function clause ext_is_CSR_defined (0x9C0, p) = haveSupMode() & (p == Machine | p == Supervisor) // sccsr