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implemented bool for writing to destination register into the rvfi output
1 parent 62132ab commit 59da05e

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2 files changed

+10
-6
lines changed

2 files changed

+10
-6
lines changed

src/cheri_insts.sail

+1-1
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,7 @@ function clause execute (CClear(q, m)) = {
783783
if q_u == 0 & i == 0 then
784784
DDC = null_cap
785785
else
786-
C(8 * q_u + i) = null_cap;
786+
wC (false, 8 * q_u + i, null_cap);
787787
RETIRE_SUCCESS
788788
}
789789

src/cheri_regs.sail

+9-5
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,8 @@ function rC r = {
103103
}
104104

105105
/* writes a register with a capability value */
106-
val wC : forall 'n, 0 <= 'n < 32. (regno('n), regtype) -> unit effect {wreg, escape}
107-
function wC (r, v) = {
106+
val wC : forall 'n, 0 <= 'n < 32. (bool, regno('n), regtype) -> unit effect {wreg, escape}
107+
function wC (b, r, v) = {
108108
match r {
109109
0 => (),
110110
1 => x1 = v,
@@ -141,17 +141,21 @@ function wC (r, v) = {
141141
_ => internal_error("Invalid capability register")
142142
};
143143
if (r != 0) then {
144-
rvfi_wX(r, v.address);
144+
if b then
145+
rvfi_wX(r, v.address);
145146
if get_config_print_reg() then
146147
print_reg("x" ^ string_of_int(r) ^ " <- " ^ RegStr(v));
147148
}
148149
}
149150

150151
function rC_bits(r: bits(5)) -> regtype = rC(unsigned(r))
151152

152-
function wC_bits(r: bits(5), v: regtype) -> unit = wC(unsigned(r), v)
153+
function wC_bits(r: bits(5), v: regtype) -> unit = wC (true, unsigned(r), v)
153154

154-
overload C = {rC_bits, wC_bits, rC, wC}
155+
val wC_rvfi : forall 'n, 0 <= 'n < 32. (regno('n), regtype) -> unit effect {wreg, escape}
156+
function wC_rvfi (r, v) = wC (true, r, v)
157+
158+
overload C = {rC_bits, wC_bits, rC, wC_rvfi}
155159

156160
val ext_init_regs : unit -> unit effect {wreg}
157161
function ext_init_regs () = {

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