From af2586b90234ea34cb66a494795881b1e4720ce6 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Fri, 19 Apr 2024 08:53:54 +0100 Subject: [PATCH 1/3] Added TIDC registers --- src/cheri_insts.sail | 5 +++++ src/cheri_regs.sail | 2 ++ src/cheri_scr_map.sail | 1 + src/cheri_sys_regs.sail | 2 ++ 4 files changed, 10 insertions(+) diff --git a/src/cheri_insts.sail b/src/cheri_insts.sail index e093b641..c7a48072 100644 --- a/src/cheri_insts.sail +++ b/src/cheri_insts.sail @@ -364,10 +364,12 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { let (specialExists, ro, priv, needASR) : (bool, bool, Privilege, bool) = match unsigned(scr) { 0 => (true, true, User, false), 1 => (true, false, User, false), + 3 if haveUsrMode() => (true, true, User, false), 4 if haveNExt() => (true, false, User, true), 5 if haveNExt() => (true, false, User, true), 6 if haveNExt() => (true, false, User, true), 7 if haveNExt() => (true, false, User, true), + 11 if haveSupMode() => (true, false, Supervisor, true), 12 if haveSupMode() => (true, false, Supervisor, true), 13 if haveSupMode() => (true, false, Supervisor, true), 14 if haveSupMode() => (true, false, Supervisor, true), @@ -395,10 +397,12 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { pcc }, 1 => DDC, + 3 => STIDC, 4 => UTCC, 5 => UTDC, 6 => UScratchC, 7 => legalize_epcc(UEPCC), + 11 => STIDC, 12 => STCC, 13 => STDC, 14 => SScratchC, @@ -416,6 +420,7 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { 5 => UTDC = cs1_val, 6 => UScratchC = cs1_val, 7 => UEPCC = cs1_val, + 12 => STIDC = cs1_val, 12 => STCC = legalize_tcc(STCC, cs1_val), 13 => STDC = cs1_val, 14 => SScratchC = cs1_val, diff --git a/src/cheri_regs.sail b/src/cheri_regs.sail index 17d3a7cb..336cbdff 100644 --- a/src/cheri_regs.sail +++ b/src/cheri_regs.sail @@ -159,11 +159,13 @@ function ext_init_regs () = { DDC = default_cap; nextPCC = default_cap; + UTIDC = null_cap; UTCC = default_cap; UTDC = null_cap; UScratchC = null_cap; UEPCC = default_cap; + STIDC = null_cap; STCC = default_cap; STDC = null_cap; SScratchC = null_cap; diff --git a/src/cheri_scr_map.sail b/src/cheri_scr_map.sail index 10aaebeb..75700b05 100644 --- a/src/cheri_scr_map.sail +++ b/src/cheri_scr_map.sail @@ -69,6 +69,7 @@ scattered mapping scr_name_map mapping clause scr_name_map = 0b00000 <-> "pcc" mapping clause scr_name_map = 0b00001 <-> "ddc" +mapping clause scr_name_map = 0b00011 <-> "utidc" mapping clause scr_name_map = 0b00100 <-> "utcc" mapping clause scr_name_map = 0b00101 <-> "utdc" mapping clause scr_name_map = 0b00110 <-> "uscratchc" diff --git a/src/cheri_sys_regs.sail b/src/cheri_sys_regs.sail index 3b871168..e68bdd63 100644 --- a/src/cheri_sys_regs.sail +++ b/src/cheri_sys_regs.sail @@ -114,10 +114,12 @@ register PCC : Capability register nextPCC : Capability register DDC : Capability +register UTIDC : Capability register UTCC : Capability register UTDC : Capability register UScratchC : Capability register UEPCC : Capability +register STIDC : Capability register STCC : Capability register STDC : Capability register SScratchC : Capability From 1f7b0e471fe9eae0e0f60dcde9113e298644ac2f Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Wed, 8 May 2024 09:07:16 +0100 Subject: [PATCH 2/3] Added updated support for xTIDC registers --- src/cheri_insts.sail | 43 +++++++++++++++++++++++------------------ src/cheri_regs.sail | 1 + src/cheri_scr_map.sail | 2 ++ src/cheri_sys_regs.sail | 1 + 4 files changed, 28 insertions(+), 19 deletions(-) diff --git a/src/cheri_insts.sail b/src/cheri_insts.sail index c7a48072..aac396d8 100644 --- a/src/cheri_insts.sail +++ b/src/cheri_insts.sail @@ -361,30 +361,34 @@ union clause ast = CSpecialRW : (regidx, screg, regidx) * **DDC** should need clearing, which can be done with [CClear]. */ function clause execute (CSpecialRW(cd, scr, cs1)) = { - let (specialExists, ro, priv, needASR) : (bool, bool, Privilege, bool) = match unsigned(scr) { - 0 => (true, true, User, false), - 1 => (true, false, User, false), - 3 if haveUsrMode() => (true, true, User, false), - 4 if haveNExt() => (true, false, User, true), - 5 if haveNExt() => (true, false, User, true), - 6 if haveNExt() => (true, false, User, true), - 7 if haveNExt() => (true, false, User, true), - 11 if haveSupMode() => (true, false, Supervisor, true), - 12 if haveSupMode() => (true, false, Supervisor, true), - 13 if haveSupMode() => (true, false, Supervisor, true), - 14 if haveSupMode() => (true, false, Supervisor, true), - 15 if haveSupMode() => (true, false, Supervisor, true), - 28 => (true, false, Machine, true), - 29 => (true, false, Machine, true), - 30 => (true, false, Machine, true), - 31 => (true, false, Machine, true), - _ => (false, true, Machine, true) + let (specialExists, ro, priv, needASR, needASRW) : (bool, bool, Privilege, bool, bool) = match unsigned(scr) { + 0 => (true, true, User, false, false), + 1 => (true, false, User, false, false), + 3 if haveUsrMode() => (true, true, User, false, true), + 4 if haveNExt() => (true, false, User, true, true), + 5 if haveNExt() => (true, false, User, true, true), + 6 if haveNExt() => (true, false, User, true, true), + 7 if haveNExt() => (true, false, User, true, true), + 11 if haveSupMode() => (true, false, Supervisor, false, true), + 12 if haveSupMode() => (true, false, Supervisor, true, true), + 13 if haveSupMode() => (true, false, Supervisor, true, true), + 14 if haveSupMode() => (true, false, Supervisor, true, true), + 15 if haveSupMode() => (true, false, Supervisor, true, true), + 27 => (true, false, Machine, false, true), + 28 => (true, false, Machine, true, true), + 29 => (true, false, Machine, true, true), + 30 => (true, false, Machine, true, true), + 31 => (true, false, Machine, true, true), + _ => (false, true, Machine, true, true) }; if (not(specialExists) | ro & cs1 != zeros() | (privLevel_to_bits(cur_privilege) <_u privLevel_to_bits(priv))) then { handle_illegal(); RETIRE_FAIL + } else if (needASRW & (cs1 != zeros()) & not(pcc_access_system_regs())) then { + handle_cheri_cap_exception(CapEx_AccessSystemRegsViolation, 0b1 @ scr); + RETIRE_FAIL } else if (needASR & not(pcc_access_system_regs())) then { handle_cheri_cap_exception(CapEx_AccessSystemRegsViolation, 0b1 @ scr); RETIRE_FAIL @@ -397,7 +401,7 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { pcc }, 1 => DDC, - 3 => STIDC, + 3 => UTIDC, 4 => UTCC, 5 => UTDC, 6 => UScratchC, @@ -407,6 +411,7 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { 13 => STDC, 14 => SScratchC, 15 => legalize_epcc(SEPCC), + 27 => MTIDC, 28 => MTCC, 29 => MTDC, 30 => MScratchC, diff --git a/src/cheri_regs.sail b/src/cheri_regs.sail index 336cbdff..7b31e790 100644 --- a/src/cheri_regs.sail +++ b/src/cheri_regs.sail @@ -171,6 +171,7 @@ function ext_init_regs () = { SScratchC = null_cap; SEPCC = default_cap; + MTIDC = null_cap; MTCC = default_cap; MTDC = null_cap; MScratchC = null_cap; diff --git a/src/cheri_scr_map.sail b/src/cheri_scr_map.sail index 75700b05..53e14b11 100644 --- a/src/cheri_scr_map.sail +++ b/src/cheri_scr_map.sail @@ -75,11 +75,13 @@ mapping clause scr_name_map = 0b00101 <-> "utdc" mapping clause scr_name_map = 0b00110 <-> "uscratchc" mapping clause scr_name_map = 0b00111 <-> "uepcc" +mapping clause scr_name_map = 0b01011 <-> "stidc" mapping clause scr_name_map = 0b01100 <-> "stcc" mapping clause scr_name_map = 0b01101 <-> "stdc" mapping clause scr_name_map = 0b01110 <-> "sscratchc" mapping clause scr_name_map = 0b01111 <-> "sepcc" +mapping clause scr_name_map = 0b11011 <-> "mtidc" mapping clause scr_name_map = 0b11100 <-> "mtcc" mapping clause scr_name_map = 0b11101 <-> "mtdc" mapping clause scr_name_map = 0b11110 <-> "mscratchc" diff --git a/src/cheri_sys_regs.sail b/src/cheri_sys_regs.sail index e68bdd63..3ee3d582 100644 --- a/src/cheri_sys_regs.sail +++ b/src/cheri_sys_regs.sail @@ -124,6 +124,7 @@ register STCC : Capability register STDC : Capability register SScratchC : Capability register SEPCC : Capability +register MTIDC : Capability register MTCC : Capability register MTDC : Capability register MScratchC : Capability From c690afa684ba9fe167b2033538f80eff0d021f58 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 9 May 2024 09:58:48 +0100 Subject: [PATCH 3/3] Added missing mappings for xTIDC registers --- src/cheri_insts.sail | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cheri_insts.sail b/src/cheri_insts.sail index aac396d8..b1e4dfac 100644 --- a/src/cheri_insts.sail +++ b/src/cheri_insts.sail @@ -421,15 +421,17 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = { if (cs1 != zeros()) then { match unsigned(scr) { 1 => DDC = cs1_val, + 3 => UTIDC = cs1_val, 4 => UTCC = legalize_tcc(UTCC, cs1_val), 5 => UTDC = cs1_val, 6 => UScratchC = cs1_val, 7 => UEPCC = cs1_val, - 12 => STIDC = cs1_val, + 11 => STIDC = cs1_val, 12 => STCC = legalize_tcc(STCC, cs1_val), 13 => STDC = cs1_val, 14 => SScratchC = cs1_val, 15 => SEPCC = cs1_val, + 27 => MTIDC = cs1_val, 28 => MTCC = legalize_tcc(MTCC, cs1_val), 29 => MTDC = cs1_val, 30 => MScratchC = cs1_val,