Logic Analyzer Signals from the FPGA itself

[cospan]

A great feature would be to read the signal names directly from the FPGA itself instead of manually naming the signals by 'aliasing highlighted trace' in GTKWave.

This would require writing a ROM within the logic analyzer that holds all the signals as an ascii string.

A possible approach would be a JSON text string can be put into this memory block, something like

{
    "signal0":"button0",
    "signal[2:1]":"led[1:0]
} 

Another issue that would need to be resolved is how to extrapolate the signal name from the configuration file. The logic analyzer connections are done within the configuration file, which can only attach to signals on the top level of the design but it isn't useful to read 'debug[0]', it would be better to read 'button0' so there needs to be a Python module that analyzes the Verilog antenna and find out where the signal is actual pointing to, so if, for example the SDRAM is being debugged and the logic analyzer is connected to mem1_debug[31:0] and mem1_debug connection looks like the following

top:mem1_debug[0] -> wb_sdram(mem1):debug[0] -> sdram(mem):debug[0] -> sdram_write(write_path):debug[0]:i_enable

The generated signal could be the correct net name for the above signal this would be:

top.mem1.mem.write_path.i_enable