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CreeeegerCreeeeger
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DEBUG: add info instead of debug level
1 parent d1f69a4 commit 81935c5

72 files changed

Lines changed: 435 additions & 435 deletions

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‎drivers/gpu/arm/bv_r38p1/backend/gpu/mali_kbase_model_dummy.c‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -966,7 +966,7 @@ static void update_job_irq_js_state(struct dummy_model_t *dummy, int mask)
966966
int i;
967967

968968
lockdep_assert_held(&hw_error_status.access_lock);
969-
pr_debug("%s", "Updating the JS_ACTIVE register");
969+
pr_info("%s", "Updating the JS_ACTIVE register");
970970

971971
for (i = 0; i < NUM_SLOTS; i++) {
972972
int slot_active = dummy->slots[i].job_active;
@@ -993,7 +993,7 @@ static void update_job_irq_js_state(struct dummy_model_t *dummy, int mask)
993993
}
994994
}
995995
}
996-
pr_debug("The new snapshot is 0x%08X\n", dummy->job_irq_js_state);
996+
pr_info("The new snapshot is 0x%08X\n", dummy->job_irq_js_state);
997997
}
998998
#endif /* !MALI_USE_CSF */
999999

@@ -1016,7 +1016,7 @@ static const struct control_reg_values_t *find_control_reg_values(const char *gp
10161016

10171017
if (!strcmp(fcrv->name, gpu)) {
10181018
ret = fcrv;
1019-
pr_debug("Found control register values for %s\n", gpu);
1019+
pr_info("Found control register values for %s\n", gpu);
10201020
break;
10211021
}
10221022
}
@@ -1163,13 +1163,13 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
11631163
}
11641164
if (addr == JOB_SLOT_REG(slot_idx, JS_COMMAND_NEXT) &&
11651165
value == 1) {
1166-
pr_debug("%s", "start detected");
1166+
pr_info("%s", "start detected");
11671167
KBASE_DEBUG_ASSERT(!dummy->slots[slot_idx].job_active ||
11681168
!dummy->slots[slot_idx].job_queued);
11691169
if ((dummy->slots[slot_idx].job_active) ||
11701170
(hw_error_status.job_irq_rawstat &
11711171
(1 << (slot_idx + 16)))) {
1172-
pr_debug("~~~~~~~~~~~ Start: job slot is already active or there are IRQ pending ~~~~~~~~~"
1172+
pr_info("~~~~~~~~~~~ Start: job slot is already active or there are IRQ pending ~~~~~~~~~"
11731173
);
11741174
dummy->slots[slot_idx].job_queued = 1;
11751175
} else {
@@ -1191,7 +1191,7 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
11911191
} else { /*value == 3 */
11921192

11931193
if (dummy->slots[slot_idx].job_disabled != 0) {
1194-
pr_debug("enabling slot after HARD_STOP"
1194+
pr_info("enabling slot after HARD_STOP"
11951195
);
11961196
dummy->slots[slot_idx].job_disabled = 0;
11971197
}
@@ -1209,7 +1209,7 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
12091209
* update_job_irq_js_state
12101210
*/
12111211
}
1212-
pr_debug("%s", "job irq cleared");
1212+
pr_info("%s", "job irq cleared");
12131213
update_job_irq_js_state(dummy, value);
12141214
/*remove error condition for JOB */
12151215
hw_error_status.job_irq_rawstat &= ~(value);
@@ -1219,27 +1219,27 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
12191219

12201220
for (i = 0; i < NUM_SLOTS; i++)
12211221
dummy->slots[i].job_irq_mask = (value >> i) & 0x01;
1222-
pr_debug("job irq mask to value %x", value);
1222+
pr_info("job irq mask to value %x", value);
12231223
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
12241224
#else /* !MALI_USE_CSF */
12251225
if (addr == JOB_CONTROL_REG(JOB_IRQ_CLEAR)) {
1226-
pr_debug("%s", "job irq cleared");
1226+
pr_info("%s", "job irq cleared");
12271227

12281228
hw_error_status.job_irq_rawstat &= ~(value);
12291229
hw_error_status.job_irq_status &= ~(value);
12301230
} else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
12311231
/* ignore JOB_IRQ_MASK as it is handled by CSFFW */
12321232
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
12331233
#endif /* !MALI_USE_CSF */
1234-
pr_debug("GPU_IRQ_MASK set to 0x%x", value);
1234+
pr_info("GPU_IRQ_MASK set to 0x%x", value);
12351235
dummy->reset_completed_mask = (value >> 8) & 0x01;
12361236
dummy->power_changed_mask = (value >> 9) & 0x03;
12371237
dummy->clean_caches_completed_irq_enabled = (value & (1u << 17)) != 0u;
12381238
} else if (addr == GPU_CONTROL_REG(COHERENCY_ENABLE)) {
12391239
dummy->coherency_enable = value;
12401240
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_CLEAR)) {
12411241
if (value & (1 << 8)) {
1242-
pr_debug("%s", "gpu RESET_COMPLETED irq cleared");
1242+
pr_info("%s", "gpu RESET_COMPLETED irq cleared");
12431243
dummy->reset_completed = 0;
12441244
}
12451245
if (value & (3 << 9))
@@ -1257,7 +1257,7 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
12571257
switch (value) {
12581258
case GPU_COMMAND_SOFT_RESET:
12591259
case GPU_COMMAND_HARD_RESET:
1260-
pr_debug("gpu reset (%d) requested", value);
1260+
pr_info("gpu reset (%d) requested", value);
12611261
/* no more fault status */
12621262
hw_error_status.gpu_fault_status = 0;
12631263
/* completed reset instantly */
@@ -1271,7 +1271,7 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
12711271
case GPU_COMMAND_CLEAN_CACHES:
12721272
case GPU_COMMAND_CLEAN_INV_CACHES:
12731273
#endif
1274-
pr_debug("clean caches requested");
1274+
pr_info("clean caches requested");
12751275
dummy->clean_caches_completed = true;
12761276
break;
12771277
#if !MALI_USE_CSF
@@ -1292,7 +1292,7 @@ u8 midgard_model_write_reg(void *h, u32 addr, u32 value)
12921292
if (addr == GPU_CONTROL_REG(CSF_HW_DOORBELL_PAGE_OFFSET))
12931293
hw_error_status.job_irq_status = JOB_IRQ_GLOBAL_IF;
12941294
} else if (addr == IPA_CONTROL_REG(COMMAND)) {
1295-
pr_debug("Received IPA_CONTROL command");
1295+
pr_info("Received IPA_CONTROL command");
12961296
} else if (addr == IPA_CONTROL_REG(TIMER)) {
12971297
ipa_control_timer_enabled = value ? true : false;
12981298
} else if ((addr >= IPA_CONTROL_REG(SELECT_CSHW_LO)) &&
@@ -1514,7 +1514,7 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15141514
*value = 0; /* 0 by default */
15151515
#if !MALI_USE_CSF
15161516
if (addr == JOB_CONTROL_REG(JOB_IRQ_JS_STATE)) {
1517-
pr_debug("%s", "JS_ACTIVE being read");
1517+
pr_info("%s", "JS_ACTIVE being read");
15181518

15191519
*value = dummy->job_irq_js_state;
15201520
} else if (addr == GPU_CONTROL_REG(GPU_ID)) {
@@ -1525,10 +1525,10 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15251525
*value = dummy->control_reg_values->gpu_id;
15261526
} else if (addr == JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)) {
15271527
*value = hw_error_status.job_irq_rawstat;
1528-
pr_debug("%s", "JS_IRQ_RAWSTAT being read");
1528+
pr_info("%s", "JS_IRQ_RAWSTAT being read");
15291529
} else if (addr == JOB_CONTROL_REG(JOB_IRQ_STATUS)) {
15301530
*value = hw_error_status.job_irq_status;
1531-
pr_debug("JS_IRQ_STATUS being read %x", *value);
1531+
pr_info("JS_IRQ_STATUS being read %x", *value);
15321532
}
15331533
#if !MALI_USE_CSF
15341534
else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
@@ -1537,7 +1537,7 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15371537
*value = 0;
15381538
for (i = 0; i < NUM_SLOTS; i++)
15391539
*value |= dummy->slots[i].job_irq_mask << i;
1540-
pr_debug("JS_IRQ_MASK being read %x", *value);
1540+
pr_info("JS_IRQ_MASK being read %x", *value);
15411541
}
15421542
#else /* !MALI_USE_CSF */
15431543
else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK))
@@ -1547,7 +1547,7 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15471547
*value = (dummy->reset_completed_mask << 8) |
15481548
((dummy->clean_caches_completed_irq_enabled ? 1u : 0u) << 17) |
15491549
(dummy->power_changed_mask << 9) | (1 << 7) | 1;
1550-
pr_debug("GPU_IRQ_MASK read %x", *value);
1550+
pr_info("GPU_IRQ_MASK read %x", *value);
15511551
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)) {
15521552
*value = (dummy->power_changed << 9) | (dummy->power_changed << 10) |
15531553
(dummy->reset_completed << 8) |
@@ -1556,7 +1556,7 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15561556
#endif /* !MALI_USE_CSF */
15571557
((dummy->clean_caches_completed ? 1u : 0u) << 17) |
15581558
hw_error_status.gpu_error_irq;
1559-
pr_debug("GPU_IRQ_RAWSTAT read %x", *value);
1559+
pr_info("GPU_IRQ_RAWSTAT read %x", *value);
15601560
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_STATUS)) {
15611561
*value = ((dummy->power_changed && (dummy->power_changed_mask & 0x1)) << 9) |
15621562
((dummy->power_changed && (dummy->power_changed_mask & 0x2)) << 10) |
@@ -1570,7 +1570,7 @@ u8 midgard_model_read_reg(void *h, u32 addr, u32 * const value)
15701570
0u)
15711571
<< 17) |
15721572
hw_error_status.gpu_error_irq;
1573-
pr_debug("GPU_IRQ_STAT read %x", *value);
1573+
pr_info("GPU_IRQ_STAT read %x", *value);
15741574
} else if (addr == GPU_CONTROL_REG(GPU_STATUS)) {
15751575
*value = 0;
15761576
#if !MALI_USE_CSF

‎drivers/gpu/arm/bv_r38p1/tests/kutf/kutf_suite.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1195,7 +1195,7 @@ static void __exit exit_kutf_core(void)
11951195
*/
11961196
static int __init init_kutf_core(void)
11971197
{
1198-
pr_debug("KUTF requires a kernel with debug fs support");
1198+
pr_info("KUTF requires a kernel with debug fs support");
11991199

12001200
return -ENODEV;
12011201
}

‎drivers/gpu/arm/bv_r38p1/tests/mali_kutf_clk_rate_trace/kernel/mali_kutf_clk_rate_trace_test.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ static const char *kutf_clk_trace_do_get_platform(
462462
platform = "GPU";
463463
}
464464

465-
pr_debug("%s - platform is %s\n", __func__, platform);
465+
pr_info("%s - platform is %s\n", __func__, platform);
466466
snprintf(portal_msg_buf, PORTAL_MSG_LEN,
467467
"{SEQ:%d, PLATFORM:%s}", seq, platform);
468468

@@ -739,7 +739,7 @@ static void mali_kutf_clk_rate_trace_test_portal(struct kutf_context *context)
739739
struct kutf_clk_rate_trace_fixture_data *data = context->fixture;
740740
struct clk_trace_portal_input new_cmd;
741741

742-
pr_debug("Test portal service start\n");
742+
pr_info("Test portal service start\n");
743743

744744
while (data->server_state == PORTAL_STATE_LIVE) {
745745
if (kutf_clk_trace_dequeue_portal_cmd(context, &new_cmd))
@@ -793,7 +793,7 @@ static void mali_kutf_clk_rate_trace_test_portal(struct kutf_context *context)
793793
else
794794
kutf_test_fail(context, data->result_msg);
795795

796-
pr_debug("Test end\n");
796+
pr_info("Test end\n");
797797
}
798798

799799
/**
@@ -812,21 +812,21 @@ static void *mali_kutf_clk_rate_trace_create_fixture(
812812
int i;
813813

814814
/* Acquire the kbase device */
815-
pr_debug("Finding device\n");
815+
pr_info("Finding device\n");
816816
kbdev = kbase_find_device(MINOR_FOR_FIRST_KBASE_DEV);
817817
if (kbdev == NULL) {
818818
kutf_test_fail(context, "Failed to find kbase device");
819819
return NULL;
820820
}
821821

822-
pr_debug("Creating fixture\n");
822+
pr_info("Creating fixture\n");
823823
data = kutf_mempool_alloc(&context->fixture_pool,
824824
sizeof(struct kutf_clk_rate_trace_fixture_data));
825825
if (!data)
826826
return NULL;
827827

828828
*data = (const struct kutf_clk_rate_trace_fixture_data){ NULL };
829-
pr_debug("Hooking up the test portal to kbdev clk rate trace\n");
829+
pr_info("Hooking up the test portal to kbdev clk rate trace\n");
830830
spin_lock(&kbdev->pm.clk_rtm.lock);
831831

832832
if (g_ptr_portal_data != NULL) {
@@ -867,11 +867,11 @@ static void *mali_kutf_clk_rate_trace_create_fixture(
867867

868868
if (data->nclks == 0) {
869869
data->server_state = PORTAL_STATE_NO_CLK;
870-
pr_debug("Kbdev has no clocks for rate trace");
870+
pr_info("Kbdev has no clocks for rate trace");
871871
} else
872872
data->server_state = PORTAL_STATE_LIVE;
873873

874-
pr_debug("Created fixture\n");
874+
pr_info("Created fixture\n");
875875

876876
return data;
877877
}
@@ -895,9 +895,9 @@ static void mali_kutf_clk_rate_trace_remove_fixture(
895895
kbase_clk_rate_trace_manager_unsubscribe(
896896
&kbdev->pm.clk_rtm, &data->listener);
897897
}
898-
pr_debug("Destroying fixture\n");
898+
pr_info("Destroying fixture\n");
899899
kbase_release_device(kbdev);
900-
pr_debug("Destroyed fixture\n");
900+
pr_info("Destroyed fixture\n");
901901
}
902902

903903
/**
@@ -911,7 +911,7 @@ static int __init mali_kutf_clk_rate_trace_test_module_init(void)
911911
unsigned int filters;
912912
union kutf_callback_data suite_data = { NULL };
913913

914-
pr_debug("Creating app\n");
914+
pr_info("Creating app\n");
915915

916916
g_ptr_portal_data = NULL;
917917
kutf_app = kutf_create_application(CLK_RATE_TRACE_APP_NAME);
@@ -922,7 +922,7 @@ static int __init mali_kutf_clk_rate_trace_test_module_init(void)
922922
return -ENOMEM;
923923
}
924924

925-
pr_debug("Create suite %s\n", CLK_RATE_TRACE_SUITE_NAME);
925+
pr_info("Create suite %s\n", CLK_RATE_TRACE_SUITE_NAME);
926926
suite = kutf_create_suite_with_filters_and_data(
927927
kutf_app, CLK_RATE_TRACE_SUITE_NAME, 1,
928928
mali_kutf_clk_rate_trace_create_fixture,
@@ -943,7 +943,7 @@ static int __init mali_kutf_clk_rate_trace_test_module_init(void)
943943
mali_kutf_clk_rate_trace_test_portal,
944944
filters);
945945

946-
pr_debug("Init complete\n");
946+
pr_info("Init complete\n");
947947
return 0;
948948
}
949949

@@ -953,9 +953,9 @@ static int __init mali_kutf_clk_rate_trace_test_module_init(void)
953953
*/
954954
static void __exit mali_kutf_clk_rate_trace_test_module_exit(void)
955955
{
956-
pr_debug("Exit start\n");
956+
pr_info("Exit start\n");
957957
kutf_destroy_application(kutf_app);
958-
pr_debug("Exit complete\n");
958+
pr_info("Exit complete\n");
959959
}
960960

961961

‎drivers/gpu/arm/bv_r38p1/tests/mali_kutf_mgm_integration_test/mali_kutf_mgm_integration_test_main.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -135,21 +135,21 @@ static void *mali_kutf_mgm_integration_create_fixture(struct kutf_context *conte
135135
struct kutf_mgm_fixture_data *data;
136136
struct kbase_device *kbdev;
137137

138-
pr_debug("Finding kbase device\n");
138+
pr_info("Finding kbase device\n");
139139
kbdev = kbase_find_device(MINOR_FOR_FIRST_KBASE_DEV);
140140
if (kbdev == NULL) {
141141
kutf_test_fail(context, "Failed to find kbase device");
142142
return NULL;
143143
}
144-
pr_debug("Creating fixture\n");
144+
pr_info("Creating fixture\n");
145145

146146
data = kutf_mempool_alloc(&context->fixture_pool, sizeof(struct kutf_mgm_fixture_data));
147147
if (!data)
148148
return NULL;
149149
data->kbdev = kbdev;
150150
data->group_id = context->fixture_index;
151151

152-
pr_debug("Fixture created\n");
152+
pr_info("Fixture created\n");
153153
return data;
154154
}
155155

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
312312
retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
313313
m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
314314

315-
pr_debug("kfd: sdma base address: 0x%x\n", retval);
315+
pr_info("kfd: sdma base address: 0x%x\n", retval);
316316

317317
return retval;
318318
}
@@ -497,7 +497,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
497497
while (true) {
498498
temp = RREG32(mmCP_HQD_IQ_TIMER);
499499
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
500-
pr_debug("HW is processing IQ\n");
500+
pr_info("HW is processing IQ\n");
501501
goto loop;
502502
}
503503
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
@@ -511,7 +511,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
511511
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
512512
>= 10)
513513
break;
514-
pr_debug("IQ timer is active\n");
514+
pr_info("IQ timer is active\n");
515515
} else
516516
break;
517517
loop:
@@ -527,7 +527,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
527527
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
528528
if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
529529
break;
530-
pr_debug("Dequeue request is pending\n");
530+
pr_info("Dequeue request is pending\n");
531531

532532
if (!retry) {
533533
pr_err("CP HQD dequeue request time out\n");

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