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| 1 | +2024-02-07 Richard Biener < [email protected]> |
| 2 | + |
| 3 | + PR tree-optimization/113796 |
| 4 | + * tree-if-conv.cc (combine_blocks): Wipe range-info before |
| 5 | + replacing PHIs and inserting predicates. |
| 6 | + |
| 7 | +2024-02-07 Roger Sayle < [email protected]> |
| 8 | + |
| 9 | + |
| 10 | + PR target/113690 |
| 11 | + * config/i386/i386-features.cc (timode_convert_cst): New helper |
| 12 | + function to convert a TImode CONST_SCALAR_INT_P to a V1TImode |
| 13 | + CONST_VECTOR. |
| 14 | + (timode_scalar_chain::convert_op): Use timode_convert_cst. |
| 15 | + (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes. |
| 16 | + Use timode_convert_cst. |
| 17 | + |
| 18 | +2024-02-07 Victor Do Nascimento < [email protected]> |
| 19 | + |
| 20 | + * config/aarch64/aarch64-sys-regs.def: Copy from Binutils. |
| 21 | + * config/aarch64/aarch64.h (AARCH64_FL_AIE): New. |
| 22 | + (AARCH64_FL_DEBUGv8p9): Likewise. |
| 23 | + (AARCH64_FL_FGT2): Likewise.Likewise. |
| 24 | + (AARCH64_FL_ITE): Likewise. |
| 25 | + (AARCH64_FL_PFAR): Likewise. |
| 26 | + (AARCH64_FL_PMUv3_ICNTR): Likewise. |
| 27 | + (AARCH64_FL_PMUv3_SS): Likewise. |
| 28 | + (AARCH64_FL_PMUv3p9): Likewise. |
| 29 | + (AARCH64_FL_RASv2): Likewise. |
| 30 | + (AARCH64_FL_S1PIE): Likewise. |
| 31 | + (AARCH64_FL_S1POE): Likewise. |
| 32 | + (AARCH64_FL_S2PIE): Likewise. |
| 33 | + (AARCH64_FL_S2POE): Likewise. |
| 34 | + (AARCH64_FL_SCTLR2): Likewise. |
| 35 | + (AARCH64_FL_SEBEP): Likewise. |
| 36 | + (AARCH64_FL_SPE_FDS): Likewise. |
| 37 | + (AARCH64_FL_TCR2): Likewise. |
| 38 | + |
| 39 | +2024-02-07 Richard Biener < [email protected]> |
| 40 | + |
| 41 | + * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): |
| 42 | + Only check whether reads are in-bound in places that are not safe. |
| 43 | + Fix dependence check. Add missing newline. Clarify comments. |
| 44 | + |
| 45 | +2024-02-07 Tamar Christina < [email protected]> |
| 46 | + |
| 47 | + PR tree-optimization/113750 |
| 48 | + * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check |
| 49 | + for single predecessor when doing early break vect. |
| 50 | + * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but |
| 51 | + after labels. |
| 52 | + |
| 53 | +2024-02-07 Tamar Christina < [email protected]> |
| 54 | + |
| 55 | + PR tree-optimization/113731 |
| 56 | + * gimple-iterator.cc (gsi_move_before): Take new parameter for update |
| 57 | + method. |
| 58 | + * gimple-iterator.h (gsi_move_before): Default new param to |
| 59 | + GSI_SAME_STMT. |
| 60 | + * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with |
| 61 | + GSI_NEW_STMT. |
| 62 | + |
| 63 | +2024-02-07 Jakub Jelinek < [email protected]> |
| 64 | + |
| 65 | + PR tree-optimization/113756 |
| 66 | + * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS, |
| 67 | + use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from |
| 68 | + of lh_bits value and mask. |
| 69 | + |
| 70 | +2024-02-07 Jakub Jelinek < [email protected]> |
| 71 | + |
| 72 | + PR tree-optimization/113753 |
| 73 | + * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with |
| 74 | + UNSIGNED rather than SIGNED. If high or needs_overflow and prec is |
| 75 | + not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec |
| 76 | + so that they start with r[half_blocks_needed] lowest bit. Fix up |
| 77 | + computation of top mask for SIGNED. |
| 78 | + |
| 79 | +2024-02-07 Pan Li < [email protected]> |
| 80 | + |
| 81 | + PR target/113766 |
| 82 | + * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust |
| 83 | + the signature of func. |
| 84 | + * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto. |
| 85 | + * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make |
| 86 | + overloaded func with empty args error. |
| 87 | + |
1 | 88 | 2024-02-06 H.J. Lu < [email protected]>
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2 | 89 |
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3 | 90 | PR target/113689
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