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| 1 | +2024-02-05 Christoph Müllner < [email protected]> |
| 2 | + |
| 3 | + * config/riscv/thead.cc (th_print_operand_address): Fix compiler |
| 4 | + warning. |
| 5 | + |
| 6 | +2024-02-05 H.J. Lu < [email protected]> |
| 7 | + |
| 8 | + PR target/113689 |
| 9 | + * config/i386/i386.cc (x86_64_select_profile_regnum): New. |
| 10 | + (x86_function_profiler): Call x86_64_select_profile_regnum to |
| 11 | + get a scratch register for large model profiling. |
| 12 | + |
| 13 | +2024-02-05 Richard Ball < [email protected]> |
| 14 | + |
| 15 | + * config/arm/arm.cc (arm_output_mi_thunk): Emit |
| 16 | + insn for bti_c when bti is enabled. |
| 17 | + |
| 18 | +2024-02-05 Xi Ruoyao < [email protected]> |
| 19 | + |
| 20 | + * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for |
| 21 | + neg. |
| 22 | + |
| 23 | +2024-02-05 Xi Ruoyao < [email protected]> |
| 24 | + |
| 25 | + * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr. |
| 26 | + (neg<mode>2): Change the mode iterator from MSA to IMSA because |
| 27 | + in FP arithmetic we cannot use (0 - x) for -x. |
| 28 | + (neg<mode>2): New define_insn to implement FP vector negation, |
| 29 | + using a bnegi instruction to negate the sign bit. |
| 30 | + |
| 31 | +2024-02-05 Richard Biener < [email protected]> |
| 32 | + |
| 33 | + PR tree-optimization/113707 |
| 34 | + * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After |
| 35 | + checking the avail set treat out-of-region defines as |
| 36 | + available. |
| 37 | + |
| 38 | +2024-02-05 Richard Biener < [email protected]> |
| 39 | + |
| 40 | + * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use |
| 41 | + the default mode when building a pointer. |
| 42 | + |
| 43 | +2024-02-05 Jakub Jelinek < [email protected]> |
| 44 | + |
| 45 | + PR tree-optimization/113737 |
| 46 | + * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH |
| 47 | + has just a single label, remove it and make single successor edge |
| 48 | + EDGE_FALLTHRU. |
| 49 | + |
| 50 | +2024-02-05 Jakub Jelinek < [email protected]> |
| 51 | + |
| 52 | + PR target/113059 |
| 53 | + * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper): |
| 54 | + Remove REG_DEAD/REG_UNUSED notes at the end of the pass before |
| 55 | + df_analyze call. |
| 56 | + |
| 57 | +2024-02-05 Richard Biener < [email protected]> |
| 58 | + |
| 59 | + PR target/113255 |
| 60 | + * config/i386/i386-expand.cc |
| 61 | + (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves): |
| 62 | + Use a new pseudo for the skipped number of bytes. |
| 63 | + |
| 64 | +2024-02-05 Monk Chiang < [email protected]> |
| 65 | + |
| 66 | + * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. |
| 67 | + * doc/invoke.texi (RISC-V Options): Add sifive-p450, |
| 68 | + sifive-p670. |
| 69 | + |
| 70 | +2024-02-05 Monk Chiang < [email protected]> |
| 71 | + |
| 72 | + * config/riscv/riscv.md: Include sifive-p400.md. |
| 73 | + * config/riscv/sifive-p400.md: New file. |
| 74 | + * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. |
| 75 | + * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): |
| 76 | + Add sifive_p400. |
| 77 | + * config/riscv/riscv.cc (sifive_p400_tune_info): New. |
| 78 | + * config/riscv/riscv.h (TARGET_SFB_ALU): Update. |
| 79 | + * doc/invoke.texi (RISC-V Options): Add sifive-p400-series |
| 80 | + |
1 | 81 | 2024-02-04 Takayuki 'January June' Suwa < [email protected]>
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2 | 82 |
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3 | 83 | * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
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