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| 1 | +2025-03-03 Andrew Carlotti < [email protected]> |
| 2 | + |
| 3 | + * common/config/aarch64/aarch64-common.cc |
| 4 | + (struct aarch64_extension_info): Add field. |
| 5 | + (aarch64_get_required_features): New. |
| 6 | + * config/aarch64/aarch64-builtins.cc |
| 7 | + (aarch64_simd_switcher::aarch64_simd_switcher): Rename to... |
| 8 | + (aarch64_target_switcher::aarch64_target_switcher): ...this, |
| 9 | + and extend to handle sve, nosimd and target pragmas. |
| 10 | + (aarch64_simd_switcher::~aarch64_simd_switcher): Rename to... |
| 11 | + (aarch64_target_switcher::~aarch64_target_switcher): ...this, |
| 12 | + and extend to handle sve, nosimd and target pragmas. |
| 13 | + (handle_arm_acle_h): Use aarch64_target_switcher. |
| 14 | + (handle_arm_neon_h): Rename switcher and pass explicit flags. |
| 15 | + (aarch64_general_init_builtins): Ditto. |
| 16 | + * config/aarch64/aarch64-protos.h |
| 17 | + (class aarch64_simd_switcher): Rename to... |
| 18 | + (class aarch64_target_switcher): ...this, and add new members. |
| 19 | + (aarch64_get_required_features): New prototype. |
| 20 | + * config/aarch64/aarch64-sve-builtins.cc |
| 21 | + (sve_switcher::sve_switcher): Delete |
| 22 | + (sve_switcher::~sve_switcher): Delete |
| 23 | + (sve_alignment_switcher::sve_alignment_switcher): New |
| 24 | + (sve_alignment_switcher::~sve_alignment_switcher): New |
| 25 | + (register_builtin_types): Use alignment switcher |
| 26 | + (init_builtins): Rename switcher. |
| 27 | + (handle_arm_neon_sve_bridge_h): Ditto. |
| 28 | + (handle_arm_sme_h): Ditto. |
| 29 | + (handle_arm_sve_h): Ditto, and use alignment switcher. |
| 30 | + * config/aarch64/aarch64-sve-builtins.h |
| 31 | + (class sve_switcher): Delete. |
| 32 | + (class sme_switcher): Delete. |
| 33 | + (class sve_alignment_switcher): New. |
| 34 | + * config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H). |
| 35 | + (aarch64-sve-builtins.o): Remove $(REG_H). |
| 36 | + |
| 37 | +2025-03-03 Richard Earnshaw < [email protected]> |
| 38 | + |
| 39 | + * config/arm/thumb1.md (split patterns for GEU and LEU): New. |
| 40 | + |
| 41 | +2025-03-03 Uros Bizjak < [email protected]> |
| 42 | + |
| 43 | + Revert: |
| 44 | + 2025-03-03 Uros Bizjak < [email protected]> |
| 45 | + |
| 46 | + * combine.cc (distribute_notes): |
| 47 | + Reverse negative logic in ternary operators. |
| 48 | + |
| 49 | +2025-03-03 Uros Bizjak < [email protected]> |
| 50 | + |
| 51 | + * combine.cc (distribute_notes): |
| 52 | + Reverse negative logic in ternary operators. |
| 53 | + |
| 54 | +2025-03-03 Uros Bizjak < [email protected]> |
| 55 | + |
| 56 | + PR rtl-optimization/118739 |
| 57 | + * combine.cc (distribute_notes) <case REG_UNUSED>: Correct the |
| 58 | + logic when the register is used by I3. |
| 59 | + |
| 60 | +2025-03-03 Martin Jambor < [email protected]> |
| 61 | + |
| 62 | + PR ipa/118785 |
| 63 | + * ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Handle non-conversion |
| 64 | + unary operations separately before doing any conversions. Check |
| 65 | + expr_type_first_operand_type_p for non-unary operations too. Fix type |
| 66 | + of op_res. |
| 67 | + |
| 68 | +2025-03-03 Richard Biener < [email protected]> |
| 69 | + |
| 70 | + PR tree-optimization/119057 |
| 71 | + * tree-vect-loop.cc (check_reduction_path): Add argument |
| 72 | + specifying whether we're analyzing the inner loop of a |
| 73 | + double reduction. Do not allow extra uses outside of the |
| 74 | + double reduction cycle in this case. |
| 75 | + (vect_is_simple_reduction): Adjust. |
| 76 | + |
| 77 | +2025-03-03 Richard Biener < [email protected]> |
| 78 | + |
| 79 | + PR ipa/119067 |
| 80 | + * ipa-devirt.cc (odr_types_equivalent_p): Check |
| 81 | + TYPE_VECTOR_SUBPARTS for vectors. |
| 82 | + |
1 | 83 | 2025-03-02 Jeff Law < [email protected]>
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2 | 84 |
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3 | 85 | PR target/118934
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