|
| 1 | +2024-02-02 Tamar Christina < [email protected]> |
| 2 | + |
| 3 | + PR tree-optimization/113588 |
| 4 | + PR tree-optimization/113467 |
| 5 | + * tree-vect-data-refs.cc |
| 6 | + (vect_analyze_data_ref_dependence): Choose correct dest and fix checks. |
| 7 | + (vect_analyze_early_break_dependences): Update comments. |
| 8 | + |
| 9 | +2024-02-02 John David Anglin < [email protected]> |
| 10 | + |
| 11 | + PR target/59778 |
| 12 | + * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR |
| 13 | + and PA_BUILTIN_SET_FPSR builtins. |
| 14 | + * (pa_builtins_icode): Declare. |
| 15 | + * (def_builtin, pa_fpu_init_builtins): New. |
| 16 | + * (pa_init_builtins): Initialize FPU builtins. |
| 17 | + * (pa_builtin_decl, pa_expand_builtin_1): New. |
| 18 | + * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and |
| 19 | + PA_BUILTIN_SET_FPSR builtins. |
| 20 | + * (pa_atomic_assign_expand_fenv): New. |
| 21 | + * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New |
| 22 | + UNSPECV constants. |
| 23 | + (get_fpsr, put_fpsr): New expanders. |
| 24 | + (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New |
| 25 | + insn patterns. |
| 26 | + |
| 27 | +2024-02-02 Juzhe-Zhong < [email protected]> |
| 28 | + |
| 29 | + PR target/113697 |
| 30 | + * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move. |
| 31 | + |
| 32 | +2024-02-02 Jonathan Wakely < [email protected]> |
| 33 | + |
| 34 | + * doc/extend.texi (Common Type Attributes): Fix typo in |
| 35 | + description of hardbool. |
| 36 | + |
| 37 | +2024-02-02 Jakub Jelinek < [email protected]> |
| 38 | + |
| 39 | + PR tree-optimization/113692 |
| 40 | + * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts |
| 41 | + from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as |
| 42 | + final_cast_p. |
| 43 | + |
| 44 | +2024-02-02 Jakub Jelinek < [email protected]> |
| 45 | + |
| 46 | + PR middle-end/113699 |
| 47 | + * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle |
| 48 | + uninitialized large/huge _BitInt SSA_NAME inputs. |
| 49 | + |
| 50 | +2024-02-02 Jakub Jelinek < [email protected]> |
| 51 | + |
| 52 | + PR middle-end/113705 |
| 53 | + * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from |
| 54 | + around wi::to_wide in order to compare value in prec precision. |
| 55 | + |
| 56 | +2024-02-02 Lehua Ding < [email protected]> |
| 57 | + |
| 58 | + Revert: |
| 59 | + 2024-02-02 Juzhe-Zhong < [email protected]> |
| 60 | + |
| 61 | + * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation. |
| 62 | + |
| 63 | +2024-02-02 Juzhe-Zhong < [email protected]> |
| 64 | + |
| 65 | + * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation. |
| 66 | + |
| 67 | +2024-02-02 Pan Li < [email protected]> |
| 68 | + |
| 69 | + * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments. |
| 70 | + (riscv_pass_by_reference): Ditto. |
| 71 | + (riscv_fntype_abi): Ditto. |
| 72 | + |
| 73 | +2024-02-02 Juzhe-Zhong < [email protected]> |
| 74 | + |
| 75 | + * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function. |
| 76 | + (pre_vsetvl::cleaup): Remove vsetvl_pre. |
| 77 | + (pre_vsetvl::remove_vsetvl_pre_insns): New function. |
| 78 | + |
| 79 | +2024-02-02 Jiahao Xu < [email protected]> |
| 80 | + |
| 81 | + * config/loongarch/larchintrin.h |
| 82 | + (__frecipe_s): Update function return type. |
| 83 | + (__frecipe_d): Ditto. |
| 84 | + (__frsqrte_s): Ditto. |
| 85 | + (__frsqrte_d): Ditto. |
| 86 | + |
| 87 | +2024-02-02 Li Wei < [email protected]> |
| 88 | + |
| 89 | + * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New. |
| 90 | + (loongarch_vector_costs::add_stmt_cost): Adjust. |
| 91 | + |
| 92 | +2024-02-02 Xi Ruoyao < [email protected]> |
| 93 | + |
| 94 | + * config/loongarch/loongarch.md (unspec): Add |
| 95 | + UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2. |
| 96 | + (la_pcrel64_two_parts): New define_insn. |
| 97 | + * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a |
| 98 | + typo in the comment. |
| 99 | + (loongarch_call_tls_get_addr): If -mcmodel=extreme |
| 100 | + -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for |
| 101 | + addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL |
| 102 | + note to allow CSE addressing __tls_get_addr. |
| 103 | + (loongarch_legitimize_tls_address): If -mcmodel=extreme |
| 104 | + -mexplicit-relocs={always,auto}, address TLS IE symbols with |
| 105 | + la_pcrel64_two_parts. |
| 106 | + (loongarch_split_symbol): If -mcmodel=extreme |
| 107 | + -mexplicit-relocs={always,auto}, address symbols with |
| 108 | + la_pcrel64_two_parts. |
| 109 | + (loongarch_output_mi_thunk): Clean up unreachable code. If |
| 110 | + -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI |
| 111 | + thunks with la_pcrel64_two_parts. |
| 112 | + |
| 113 | +2024-02-02 Lulu Cheng < [email protected]> |
| 114 | + |
| 115 | + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): |
| 116 | + Add support for call36. |
| 117 | + |
| 118 | +2024-02-02 Lulu Cheng < [email protected]> |
| 119 | + |
| 120 | + * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p): |
| 121 | + When the code model of the symbol is extreme and -mexplicit-relocs=auto, |
| 122 | + the macro instruction loading symbol address is not applicable. |
| 123 | + (loongarch_call_tls_get_addr): Adjust code. |
| 124 | + (loongarch_legitimize_tls_address): Likewise. |
| 125 | + |
| 126 | +2024-02-02 Lulu Cheng < [email protected]> |
| 127 | + |
| 128 | + * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p): |
| 129 | + Add function declaration. |
| 130 | + * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p): |
| 131 | + For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend" |
| 132 | + is not allowed |
| 133 | + (loongarch_load_tls): Added macro support in extreme mode. |
| 134 | + (loongarch_call_tls_get_addr): Likewise. |
| 135 | + (loongarch_legitimize_tls_address): Likewise. |
| 136 | + (loongarch_force_address): Likewise. |
| 137 | + (loongarch_legitimize_move): Likewise. |
| 138 | + (loongarch_output_mi_thunk): Likewise. |
| 139 | + (loongarch_option_override_internal): Remove the code that detects |
| 140 | + explicit relocs status. |
| 141 | + (loongarch_handle_model_attribute): Likewise. |
| 142 | + * config/loongarch/loongarch.md (movdi_symbolic_off64): New template. |
| 143 | + * config/loongarch/predicates.md (symbolic_off64_operand): New predicate. |
| 144 | + (symbolic_off64_or_reg_operand): Likewise. |
| 145 | + |
| 146 | +2024-02-02 Lulu Cheng < [email protected]> |
| 147 | + |
| 148 | + * config/loongarch/loongarch.cc (loongarch_load_tls): |
| 149 | + Load all types of tls symbols through one function. |
| 150 | + (loongarch_got_load_tls_gd): Delete. |
| 151 | + (loongarch_got_load_tls_ld): Delete. |
| 152 | + (loongarch_got_load_tls_ie): Delete. |
| 153 | + (loongarch_got_load_tls_le): Delete. |
| 154 | + (loongarch_call_tls_get_addr): Modify the called function name. |
| 155 | + (loongarch_legitimize_tls_address): Likewise. |
| 156 | + * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete. |
| 157 | + (@load_tls<mode>): New template. |
| 158 | + (@got_load_tls_ld<mode>): Delete. |
| 159 | + (@got_load_tls_le<mode>): Delete. |
| 160 | + (@got_load_tls_ie<mode>): Delete. |
| 161 | + |
| 162 | +2024-02-02 Lulu Cheng < [email protected]> |
| 163 | + |
| 164 | + * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function. |
| 165 | + (loongarch_legitimize_address): Add logical transformation code. |
| 166 | + |
1 | 167 | 2024-02-01 Marek Polacek < [email protected]>
|
2 | 168 |
|
3 | 169 | * doc/invoke.texi: Update -Wdangling-reference documentation.
|
|
0 commit comments