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| 1 | +2024-02-15 David Faust < [email protected]> |
| 2 | + |
| 3 | + * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to |
| 4 | + use ldxb instead of ldxh. |
| 5 | + |
| 6 | +2024-02-15 Jakub Jelinek < [email protected]> |
| 7 | + |
| 8 | + PR middle-end/113921 |
| 9 | + * cfgrtl.h (prepend_insn_to_edge): New declaration. |
| 10 | + * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function |
| 11 | + comment. |
| 12 | + (prepend_insn_to_edge): New function. |
| 13 | + * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of |
| 14 | + insert_insn_on_edge. |
| 15 | + |
| 16 | +2024-02-15 Richard Biener < [email protected]> |
| 17 | + |
| 18 | + PR tree-optimization/111156 |
| 19 | + * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look |
| 20 | + at the pattern stmt if any. |
| 21 | + |
| 22 | +2024-02-15 Georg-Johann Lay < [email protected]> |
| 23 | + |
| 24 | + PR target/113927 |
| 25 | + * config/avr/avr.h (AVR_HAVE_ADIW): New macro. |
| 26 | + * config/avr/avr-protos.h (avr_adiw_reg_p): New proto. |
| 27 | + * config/avr/avr.cc (avr_adiw_reg_p): New function. |
| 28 | + (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS. |
| 29 | + Replace test_hard_reg_class (ADDW_REGS, ...) with calls to |
| 30 | + * config/avr/avr.md: Same. |
| 31 | + (attr "isa") <tiny, no_tiny>: Remove. |
| 32 | + <adiw, no_adiw>: Add. |
| 33 | + (define_insn, define_insn_and_split): When an alternative has |
| 34 | + constraint "w", then set attribute "isa" to "adiw". |
| 35 | + * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]: |
| 36 | + Built-in define __AVR_HAVE_ADIW__. |
| 37 | + * doc/invoke.texi (AVR Options): Document it. |
| 38 | + |
| 39 | +2024-02-15 Andrew Stubbs < [email protected]> |
| 40 | + |
| 41 | + * config/gcn/gcn-valu.md |
| 42 | + (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA. |
| 43 | + * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation |
| 44 | + details are supported on RDNA devices. |
| 45 | + |
| 46 | +2024-02-15 Andrew Pinski < [email protected]> |
| 47 | + |
| 48 | + PR middle-end/113508 |
| 49 | + * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m}, |
| 50 | + usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3, |
| 51 | + smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3): |
| 52 | + Add sentence about what the mode m is. |
| 53 | + |
| 54 | +2024-02-15 Andrew Pinski < [email protected]> |
| 55 | + |
| 56 | + * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs, |
| 57 | + smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the |
| 58 | + var. |
| 59 | + |
| 60 | +2024-02-15 Richard Biener < [email protected]> |
| 61 | + |
| 62 | + * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug |
| 63 | + stmts. |
| 64 | + |
| 65 | +2024-02-15 Jakub Jelinek < [email protected]> |
| 66 | + |
| 67 | + PR tree-optimization/113567 |
| 68 | + * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge |
| 69 | + _BitInt multiplication, division or modulo with |
| 70 | + SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2 |
| 71 | + force the affected inputs into a new SSA_NAME. |
| 72 | + |
1 | 73 | 2024-02-14 Uros Bizjak < [email protected]>
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2 | 74 |
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3 | 75 | PR target/113871
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