Effect-Box-PCB/Effect-Box.sch at master · DMPRO-Gruppe-B/Effect-Box-PCB · GitHub

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EESchema Schematic File Version 4
LIBS:Effect-Box-cache
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 5
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1500 1400 2200 2200
U 5D7D43D9
F0 "FPGA" 50
F1 "FPGA.sch" 50
F2 "SCLK" I R 3700 1650 50
F3 "MOSI" I R 3700 1850 50
F4 "MISO" I R 3700 2050 50
F5 "SS" I R 3700 2250 50
F6 "GPIO_0" I R 3700 2450 50
F7 "GPIO_1" I R 3700 2650 50
F8 "GPIO_2" I R 3700 2850 50
F9 "GPIO_3" I R 3700 3050 50
F10 "PROGRAM_B" I R 3700 3250 50
F11 "DONE" I R 3700 3450 50
$EndSheet
$Sheet
S 1550 4950 2150 1550
U 5D7D4441
F0 "Power supply" 50
F1 "power.sch" 50
$EndSheet
Wire Wire Line
	6000 1650 3700 1650
Wire Wire Line
	6000 1850 3700 1850
Wire Wire Line
	6000 2050 3700 2050
Wire Wire Line
	6000 2250 3700 2250
Wire Wire Line
	3700 2450 6000 2450
Wire Wire Line
	6000 2650 3700 2650
Wire Wire Line
	3700 2850 6000 2850
Wire Wire Line
	6000 3050 3700 3050
$Sheet
S 6000 1200 1450 2600
U 5D7D441F
F0 "Microcontroller" 50
F1 "microcontroller.sch" 50
F2 "USART2_TX" I L 6000 1850 50
F3 "USART2_RX" I L 6000 2050 50
F4 "USART2_CLK" I L 6000 1650 50
F5 "USART2_CS" I L 6000 2250 50
F6 "GPIO_0" I L 6000 2450 50
F7 "GPIO_1" I L 6000 2650 50
F8 "GPIO_2" I L 6000 2850 50
F9 "GPIO_3" I L 6000 3050 50
F10 "PROGRAM_B" I L 6000 3250 50
F11 "DONE" I L 6000 3450 50
$EndSheet
Wire Wire Line
	3700 3250 6000 3250
Wire Wire Line
	6000 3450 3700 3450
$EndSCHEMATC