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dma/hisi_acc: add control path operations
This commit adds control path ops for Hisilicon accelerator DMA driver. Signed-off-by: Chengwen Feng <[email protected]>
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‎doc/guides/dmadevs/hisi_acc.rst‎

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Original file line numberDiff line numberDiff line change
@@ -43,3 +43,13 @@ named ``hisi_zip-0-dma0`` and ``hisi_zip-0-dma1``.
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user could query API and algorithms,
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this driver can only match the device whose API is ``hisi_qm_v5``
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and algorithms contain ``udma``.
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Device Configuration
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~~~~~~~~~~~~~~~~~~~~~
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Configuration requirements:
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* ``ring_size`` obtained from UACCE API and is a fixed value.
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* Only one ``vchan`` is supported per ``dmadev``.
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* Silent mode is not supported.
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* The transfer direction must be set to ``RTE_DMA_DIR_MEM_TO_MEM``.

‎drivers/dma/hisi_acc/hisi_acc_dmadev.c‎

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Original file line numberDiff line numberDiff line change
@@ -34,6 +34,190 @@ RTE_LOG_REGISTER_DEFAULT(hacc_dma_logtype, INFO);
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#define HACC_DMA_ERR(hw, ...) \
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HACC_DMA_DEV_LOG(hw, ERR, __VA_ARGS__)
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static int
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hacc_dma_info_get(const struct rte_dma_dev *dev,
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struct rte_dma_info *dev_info,
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uint32_t info_sz)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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RTE_SET_USED(info_sz);
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dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
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RTE_DMA_CAPA_SVA |
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RTE_DMA_CAPA_OPS_COPY |
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RTE_DMA_CAPA_OPS_FILL;
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dev_info->max_vchans = 1;
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dev_info->max_desc = hw->sq_depth;
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dev_info->min_desc = hw->sq_depth;
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return 0;
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}
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static int
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hacc_dma_configure(struct rte_dma_dev *dev,
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const struct rte_dma_conf *conf,
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uint32_t conf_sz)
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{
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RTE_SET_USED(dev);
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RTE_SET_USED(conf);
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RTE_SET_USED(conf_sz);
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return 0;
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}
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static int
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hacc_dma_start(struct rte_dma_dev *dev)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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int ret;
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if ((*hw->sq_status != 0) || (*hw->cq_status != 0)) {
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HACC_DMA_ERR(hw, "detect dev is abnormal!");
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return -EIO;
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}
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if (hw->started) {
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hw->ridx = 0;
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hw->cridx = 0;
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return 0;
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}
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memset(hw->sqe, 0, hw->sqe_size * hw->sq_depth);
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memset(hw->cqe, 0, sizeof(struct hacc_dma_cqe) * hw->cq_depth);
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memset(hw->status, 0, sizeof(uint16_t) * hw->sq_depth);
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hw->ridx = 0;
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hw->cridx = 0;
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hw->sq_head = 0;
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hw->sq_tail = 0;
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hw->cq_sq_head = 0;
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hw->avail_sqes = hw->sq_depth - HACC_DMA_SQ_GAP_NUM - 1;
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hw->cq_head = 0;
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hw->cqs_completed = 0;
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hw->cqe_vld = 1;
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hw->submitted = 0;
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hw->completed = 0;
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hw->errors = 0;
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hw->invalid_lens = 0;
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hw->qfulls = 0;
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ret = rte_uacce_queue_start(&hw->qctx);
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if (ret == 0)
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hw->started = true;
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return ret;
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}
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static int
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hacc_dma_stop(struct rte_dma_dev *dev)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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if ((*hw->sq_status != 0) || (*hw->cq_status != 0)) {
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/* This indicates that the dev is abnormal. The correct error handling
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* is to close the dev (so that kernel module will perform error handling)
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* and apply for a new dev.
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* If an error code is returned here, the dev cannot be closed. Therefore,
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* zero is returned and an error trace is added.
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*/
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HACC_DMA_ERR(hw, "detect dev is abnormal!");
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return 0;
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}
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return 0;
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}
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static int
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hacc_dma_close(struct rte_dma_dev *dev)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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/* The dmadev already stopped */
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rte_free(hw->status);
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rte_uacce_queue_unmap(&hw->qctx, RTE_UACCE_QFRT_DUS);
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rte_uacce_queue_unmap(&hw->qctx, RTE_UACCE_QFRT_MMIO);
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rte_uacce_queue_free(&hw->qctx);
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return 0;
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}
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static int
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hacc_dma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
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const struct rte_dma_vchan_conf *conf,
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uint32_t conf_sz)
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{
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RTE_SET_USED(dev);
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RTE_SET_USED(vchan);
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RTE_SET_USED(conf);
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RTE_SET_USED(conf_sz);
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return 0;
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}
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static int
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hacc_dma_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,
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struct rte_dma_stats *stats,
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uint32_t stats_sz)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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RTE_SET_USED(vchan);
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RTE_SET_USED(stats_sz);
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stats->submitted = hw->submitted;
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stats->completed = hw->completed;
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stats->errors = hw->errors;
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return 0;
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}
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static int
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hacc_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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RTE_SET_USED(vchan);
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hw->submitted = 0;
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hw->completed = 0;
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hw->errors = 0;
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hw->invalid_lens = 0;
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hw->io_errors = 0;
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hw->qfulls = 0;
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return 0;
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}
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static int
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hacc_dma_dump(const struct rte_dma_dev *dev, FILE *f)
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{
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struct hacc_dma_dev *hw = dev->data->dev_private;
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fprintf(f, " sqn: %u sq_status: %s cq_status: %s\n"
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" sqe_size: %u sq_depth: %u sq_depth_mask: %u cq_depth: %u\n",
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hw->sqn, (*hw->sq_status != 0) ? "ERR" : "OK",
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(*hw->cq_status != 0) ? "ERR" : "OK",
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hw->sqe_size, hw->sq_depth, hw->sq_depth_mask, hw->cq_depth);
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fprintf(f, " ridx: %u cridx: %u\n"
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" sq_head: %u sq_tail: %u cq_sq_head: %u avail_sqes: %u\n"
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" cq_head: %u cqs_completed: %u cqe_vld: %u\n",
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hw->ridx, hw->cridx,
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hw->sq_head, hw->sq_tail, hw->cq_sq_head, hw->avail_sqes,
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hw->cq_head, hw->cqs_completed, hw->cqe_vld);
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fprintf(f, " submitted: %" PRIu64 " completed: %" PRIu64 " errors: %" PRIu64
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" invalid_lens: %" PRIu64 " io_errors: %" PRIu64 " qfulls: %" PRIu64 "\n",
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hw->submitted, hw->completed, hw->errors, hw->invalid_lens,
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hw->io_errors, hw->qfulls);
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return 0;
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}
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static const struct rte_dma_dev_ops hacc_dmadev_ops = {
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.dev_info_get = hacc_dma_info_get,
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.dev_configure = hacc_dma_configure,
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.dev_start = hacc_dma_start,
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.dev_stop = hacc_dma_stop,
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.dev_close = hacc_dma_close,
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.vchan_setup = hacc_dma_vchan_setup,
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.stats_get = hacc_dma_stats_get,
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.stats_reset = hacc_dma_stats_reset,
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.dev_dump = hacc_dma_dump,
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};
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static void
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hacc_dma_gen_dev_name(const struct rte_uacce_device *uacce_dev,
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uint16_t queue_id, char *dev_name, size_t size)
@@ -111,6 +295,7 @@ hacc_dma_create(struct rte_uacce_device *uacce_dev, uint16_t queue_id)
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}
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dev->device = &uacce_dev->device;
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dev->dev_ops = &hacc_dmadev_ops;
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dev->fp_obj->dev_private = dev->data->dev_private;
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hw = dev->data->dev_private;

‎drivers/dma/hisi_acc/hisi_acc_dmadev.h‎

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Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@
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#define HACC_DMA_DEVARG_QUEUES "queues"
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#define HACC_DMA_DEFAULT_QUEUES 1
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#define HACC_DMA_CQ_DOORBELL_PACE 64
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#define HACC_DMA_SQ_GAP_NUM HACC_DMA_CQ_DOORBELL_PACE
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struct hacc_dma_config {
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uint16_t queues;
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@@ -38,7 +41,45 @@ struct hacc_dma_dev {
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uint16_t sqn; /**< SQ global number, inited when created. */
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uint16_t sq_depth_mask; /**< SQ depth - 1, the SQ depth is power of 2. */
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uint16_t ridx; /**< ring index which will assign to the next request. */
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uint16_t cridx; /**< ring index which returned by completed APIs. */
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/**
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* SQE array management fields:
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*
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* -----------------------------------------------------
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* | SQE0 | SQE1 | SQE2 | ... | SQEx | ... | SQEn-1 |
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* -----------------------------------------------------
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* ^ ^ ^
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* | | |
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* sq_head cq_sq_head sq_tail
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*
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* sq_head: next index to the oldest completed request, this filed was
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* updated by completed* APIs.
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* sq_tail: index of the next new request, this field was updated by
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* copy or fill API.
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* cq_sq_head: next index of index that has been completed by hardware,
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* this filed was updated by completed* APIs.
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*
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* [sq_head, cq_sq_head): the SQEs that hardware already completed.
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* [cq_sq_head, sq_tail): the SQEs that hardware processing.
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*/
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uint16_t sq_head;
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uint16_t sq_tail;
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uint16_t cq_sq_head;
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uint16_t avail_sqes;
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uint16_t cq_depth; /**< CQ depth, inited when created. */
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uint16_t cq_head; /**< CQ index for next scans. */
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uint16_t cqs_completed; /**< accumulated number of completed CQs. */
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uint8_t cqe_vld; /**< valid bit for CQE, will change for every round. */
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uint64_t submitted;
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uint64_t completed;
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uint64_t errors;
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uint64_t invalid_lens;
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uint64_t io_errors;
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uint64_t qfulls;
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/**
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* The following fields are not accessed in the I/O path, so they are
@@ -50,6 +91,7 @@ struct hacc_dma_dev {
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void *dus_base;
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uint32_t sqe_size;
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uint16_t sq_depth;
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bool started;
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};
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#endif /* HISI_ACC_DMADEV_H */

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