Bug Report Content
Description
The current build system for causal-conv1d assumes an NVIDIA/CUDA environment, blocking native compilation on the
new AMD RDNA 4 architecture (gfx1201 / RX 9070 XT) under ROCm 7.2. While the hardware is capable of running these
operators, the setup.py and C++ source files contain hardcoded CUDA checks.
Environment
- Hardware: AMD Radeon RX 9070 XT (RDNA 4 / gfx1201)
- OS: Ubuntu 22.04 LTS
- ROCm Version: 7.2.0
- PyTorch Version: 2.4.0 (Custom compiled for gfx1201)
Observed Failures
- Setup Script: setup.py calls torch.cuda.get_device_capability(), which is undefined or errors out on AMD,
halting the build.
- Compiler Flags: The build system attempts to pass -gencode flags which are nvcc-specific and unrecognized by
amdclang++.
- Source Hardcoding: Files in csrc/ explicitly include <cuda_runtime.h> and use CUDA synchronization primitives
like __syncthreads() without ROCm/HIP alternatives.
Proposed Solution
- Add ROCm awareness to setup.py by checking torch.version.hip.
- Implement a macro wrapper to conditionally include <hip/hip_runtime.h> when USE_ROCM=1 is set.
- Update the build logic to support amdclang++ compiler flags for the gfx1201 target.
Impact
This blocks the usage of Mamba and Mamba-2 architectures on the latest generation of consumer AMD hardware,
despite the hardware having excellent BF16 and FP8 throughput.
Bug Report Content
Description
The current build system for causal-conv1d assumes an NVIDIA/CUDA environment, blocking native compilation on the
new AMD RDNA 4 architecture (gfx1201 / RX 9070 XT) under ROCm 7.2. While the hardware is capable of running these
operators, the setup.py and C++ source files contain hardcoded CUDA checks.
Environment
Observed Failures
halting the build.
amdclang++.
like __syncthreads() without ROCm/HIP alternatives.
Proposed Solution
Impact
This blocks the usage of Mamba and Mamba-2 architectures on the latest generation of consumer AMD hardware,
despite the hardware having excellent BF16 and FP8 throughput.