mb/novacustom/mtl-h/ramstage.c: Fix Type-C to Type-A conversion

The EnableTcssCovTypeA UPD definitions changed compared to the
ADL/RPL FSP and the PCH XHCI port being mapped is not in a
separate UPD anymore. Instead, it is passed in the same field
as (previously boolean UINT8) EnableTcssCovTypeA.

Signed-off-by: Michał Żygowski <[email protected]>

Author: miczyg1

src/mainboard/novacustom/mtl-h/ramstage.c

@@ -261,7 +261,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
 	params->CnviClkreqPinMux = 0x394CE605;  // GPP_F5
 
-	params->EnableTcssCovTypeA[1] = 1;
+	/*
+	 * [3:0] MappingPchXhciUsbA (1-based USB2 port numbering)
+	 * [5:4] Reserved
+	 * [6]   Orientation - TCSS port uses TX0/RX0 pairs or TX1/RX1 pairs
+	 * [7]   Enable
+	 */
+	params->EnableTcssCovTypeA[1] = 0x82;
 
 	/* Disable S0i2.x due to wake issues */
 	params->PmcLpmS0ixSubStateEnableMask = BIT(0);