@@ -57,33 +57,33 @@ chip soc/intel/alderlake
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"M2_1" "SlotDataBusWidth4X"
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end
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device ref xhci on
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- register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2 )" # USB-C LAN_USB1
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- register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1 )" # MSI MYSTIC LIGHT
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- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0 )" # USB-A LAN_USB1
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- register "usb2_ports[3]" = "USB2_PORT_LONG(OC0 )" # JUSB5
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- register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3 )" # HUB to rear USB 2.0
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- register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
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- register "usb2_ports[6]" = "USB2_PORT_LONG(OC7 )" # JUSB4
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- register "usb2_ports[7]" = "USB2_PORT_LONG(OC0 )" # JUSB4
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- register "usb2_ports[8]" = "USB2_PORT_LONG(OC2 )" # JUSB3
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- register "usb2_ports[9]" = "USB2_PORT_LONG(OC7 )" # JUSB3
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- register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0 )" # PS2_USB1
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- register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0 )" # PS2_USB1
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- register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0 )" # HUB to USB 2.0 headers
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- register "usb2_ports[13]" = "USB2_PORT_SHORT (OC6)" # CNVi BT
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+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0 )" # USB-C LAN_USB1
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+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0 )" # MSI MYSTIC LIGHT
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+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC1 )" # USB-A LAN_USB1
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+ register "usb2_ports[3]" = "USB2_PORT_LONG(OC1 )" # JUSB5
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+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2 )" # HUB to rear USB 2.0
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+ register "usb2_ports[5]" = "USB2_PORT_EMPTY"
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+ register "usb2_ports[6]" = "USB2_PORT_LONG(OC3 )" # JUSB4
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+ register "usb2_ports[7]" = "USB2_PORT_LONG(OC3 )" # JUSB4
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+ register "usb2_ports[8]" = "USB2_PORT_LONG(OC4 )" # JUSB3
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+ register "usb2_ports[9]" = "USB2_PORT_LONG(OC4 )" # JUSB3
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+ register "usb2_ports[10]" = "USB2_PORT_LONG(OC5 )" # PS2_USB1
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+ register "usb2_ports[11]" = "USB2_PORT_LONG(OC5 )" # PS2_USB1
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+ register "usb2_ports[12]" = "USB2_PORT_MID(OC6 )" # HUB to USB 2.0 headers
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+ register "usb2_ports[13]" = "USB2_PORT_LONG (OC6)" # CNVi BT
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register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
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register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
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- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2 )" # USB-C LAN_USB1
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- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2 )" # USB-A LAN_USB1
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- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3 )" # JUSB5
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- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0 )" # USB-A USB2
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- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7 )" # USB-A USB2
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- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7 )" # JUSB4
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- register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2 )" # JUSB4
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- register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2 )" # JUSB3
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- register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0 )" # JUSB3
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- register "usb3_ports[9]" = "USB3_PORT_EMPTY"
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+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0 )" # USB-C Gen2x2 LAN_USB1
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+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0 )" # USB-C Gen2x2 LAN_USB1
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+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1 )" # USB-A LAN_USB1
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+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1 )" # JUSB5
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+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2 )" # USB-A USB2
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+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2 )" # USB-A USB2
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+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC3 )" # JUSB4
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+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC3 )" # JUSB4
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+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC4 )" # JUSB3
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+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC4)" # JUSB3
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end
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device ref cnvi_wifi on
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# Enable CNVi BT
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