diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 4da1d807135..271aead793c 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -169,12 +169,13 @@ IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom endif $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) - $(MAKE) -C payloads/external/edk2 DasharoPayloadPkg \ + $(MAKE) -C payloads/external/edk2 \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \ CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \ CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \ + CONFIG_EDK2_DASHAROPAYLOAD=$(CONFIG_EDK2_DASHAROPAYLOAD) \ CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \ CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \ CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 1298ca90a46..0280eeb22f2 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -4,14 +4,14 @@ if PAYLOAD_EDK2 config PAYLOAD_FILE string "edk2 binary" - default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD + default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD || EDK2_DASHAROPAYLOAD default "$(obj)/ShimmedUniversalPayload.elf" if EDK2_UNIVERSAL_PAYLOAD help The result of a UefiPayloadPkg build choice prompt "EDK II build type" - default EDK2_UEFIPAYLOAD + default EDK2_DASHAROPAYLOAD help Select the build type for edk2. UniversalPayload is recommended, as it is replacing UefiPayloadPkg. Whilst in the transition phase between the two, @@ -22,6 +22,11 @@ config EDK2_UEFIPAYLOAD help Build the standard UefiPayloadPkg +config EDK2_DASHAROPAYLOAD + bool "Build DasharoPayloadPkg" + help + Build the DasharoPayloadPkg + config EDK2_UNIVERSAL_PAYLOAD bool "Build Universal Payload" help diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 57e50dd5dc4..f752c848bda 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -26,11 +26,16 @@ endif OBJCOPY = $(GCC_PREFIX)objcopy +ifeq ($(CONFIG_EDK2_DASHAROPAYLOAD),y) PAYLOAD_NAME=DasharoPayloadPkg +BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc +endif ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y) +PAYLOAD_NAME=UefiPayloadPkg BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc endif + BUILD_STR += -t COREBOOT BUILD_STR += -D BOOTLOADER=COREBOOT ifneq ($(V),1) diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index bad9d9c53e6..9efdce6bc52 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -268,7 +268,7 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_port55_read(step->reg); case IOSF_PORT_0x58: return iosf_port58_read(step->reg); - case IOSF_PORT_0x59: + case IOSF_PORT_OTG: return iosf_port59_read(step->reg); case IOSF_PORT_0x5a: return iosf_port5a_read(step->reg); @@ -336,7 +336,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_0x58: iosf_port58_write(step->reg, step->value); break; - case IOSF_PORT_0x59: + case IOSF_PORT_OTG: iosf_port59_write(step->reg, step->value); break; case IOSF_PORT_0x5a: diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl index 7d1b0a91168..de4da78f95a 100644 --- a/src/mainboard/intel/minnowmax/acpi/mainboard.asl +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -17,3 +17,13 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0C")) } } + +Scope(\_GPE) +{ + /* PMC_WAKE_PCIE0 connected to LAN on RP3 */ + Method (_L03) + { + PWS0 = 1 + Notify (\_SB.PCI0.RP03, 0x02) + } +} diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 4d3d5d93229..758a254be4e 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -29,15 +29,13 @@ chip soc/intel/baytrail register "sdcard_cap_low" = "0x076864b2" register "sdcard_cap_high" = "0x0" - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" + register "lpe_acpi_mode" = "1" register "lpss_acpi_mode" = "1" register "scc_acpi_mode" = "1" + register "otg_acpi_mode" = "1" # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 9cfa9894fcd..25a78fdf36e 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -41,6 +41,7 @@ ramstage-y += lpe.c ramstage-y += lpss.c ramstage-y += memmap.c ramstage-y += northcluster.c +ramstage-y += otg.c ramstage-y += pcie.c ramstage-y += perf_power.c ramstage-y += pmutil.c diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index f24fe7f5b7a..80a39ec897f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -156,8 +156,12 @@ static void generate_p_state_entries(int core) vid_max = pattrs->iacore_vids[IACORE_MAX]; vid_min = pattrs->iacore_vids[IACORE_LFM]; - /* Set P-states coordination type based on MSR disable bit */ - coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; + /* + * Set P-states coordination type based on MSR disable bit. + * We disable SINGLE_PCTL and INDP_AUTOCM in core_msr_script, + * so we can only use HW_ALL(using MIN_CLIP) per BWG. + */ + coord_type = HW_ALL; /* Max Non-Turbo Frequency */ clock_max = (ratio_max * pattrs->bclk_khz) / 1000; @@ -175,7 +179,7 @@ static void generate_p_state_entries(int core) acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(0, pattrs->num_cpus, coord_type); /* Add P-state entries in _PSS table */ acpigen_write_name("_PSS"); diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index d570788985d..ebc0011c8d4 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -22,6 +22,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve) C1EN, 8, /* SDIO Enable */ C2EN, 8, /* SD Card Enable */ LPEN, 8, /* LPE Enable */ + UOEN, 8, /* USB OTG Enable */ /* BAR 0 */ @@ -43,6 +44,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve) C1B0, 32, /* SDIO BAR0 */ C2B0, 32, /* SD Card BAR0 */ LPB0, 32, /* LPE BAR0 */ + UOB0, 32, /* USB OTG BAR0 */ /* BAR 1 */ @@ -64,6 +66,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve) C1B1, 32, /* SDIO BAR1 */ C2B1, 32, /* SD Card BAR1 */ LPB1, 32, /* LPE BAR1 */ + UOB1, 32, /* USB OTG BAR1 */ /* Extra */ diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index d97b85c450c..598081cfa38 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -95,3 +95,80 @@ Device (GPSS) Return (0xF) } } + +Device (GPED) +{ + Name (_HID, "INT0002") + Name (_CID, "INT0002") + Name (_DDN, "Virtual GPIO controller") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 9 } + }) + + Method (_CRS, 0, Serialized) + { + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0) + } + + Name (GBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDown, 0x0000, + "\\_SB.GPED", 0x00, ResourceConsumer,,) { 2 } + }) + + Method (_AEI, 0, Serialized) + { + Return (GBUF) + } + + Method (_E02, 0, NotSerialized) + { + If (PWBS) + { + PWBS = 1 + } + + If (PMEB) + { + PMEB = 1 + } + + If (\_SB.PCI0.SATA.PMES) + { + \_SB.PCI0.SATA.PMES = 1 + Notify (\_SB.PCI0.SATA, 0x02) + } + + If (\_SB.PCI0.EM45.PMES && (\C0EN == 0)) + { + \_SB.PCI0.EM45.PMES = 1 + Notify (\_SB.PCI0.EM45, 0x02) + } + + If (\_SB.PCI0.HDA.PMES) + { + \_SB.PCI0.HDA.PMES = 1 + Notify (\_SB.PCI0.HDA, 0x02) + } + + If (\_SB.PCI0.XHCI.PMES) + { + \_SB.PCI0.XHCI.PMES = 1 + Notify (\_SB.PCI0.XHCI, 0x02) + } + + If (\_SB.PCI0.SEC0.PMES == 1) + { + \_SB.PCI0.SEC0.PMES |= 0 + Notify (\_SB.PCI0.SEC0, 0x02) + } + } +} diff --git a/src/soc/intel/baytrail/acpi/hda.asl b/src/soc/intel/baytrail/acpi/hda.asl new file mode 100644 index 00000000000..b7fee9acf0b --- /dev/null +++ b/src/soc/intel/baytrail/acpi/hda.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(HDA) +{ + Name(_ADR,0x001b0000) + + OperationRegion (PMEB, PCI_Config, 0x74, 0x04) + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, + , 6, + PMES, 1 + } +} diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 69e1f27d253..1287998b261 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -44,7 +44,6 @@ Device (LPCB) }) } -#if !CONFIG(DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) @@ -60,7 +59,6 @@ Device (LPCB) Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400) }) } -#endif Device(PIC) /* 8259 Interrupt Controller */ { @@ -130,6 +128,16 @@ Device (LPCB) }) } + Device (FPU) /* x87-compatible Floating Point Processing Unit */ + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x01) + IRQNoFlags () {13} + }) + } + #if CONFIG(ENABLE_BUILTIN_COM1) Device (COM1) { Name (_HID, EISAID ("PNP0501")) diff --git a/src/soc/intel/baytrail/acpi/otg.asl b/src/soc/intel/baytrail/acpi/otg.asl new file mode 100644 index 00000000000..15deed87f83 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/otg.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (OTG) +{ + Name (_HID, "80860F37") + Name (_CID, "80860F37") + Name (_UID, 1) + Name (_DDN, "USB OTG Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) + Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) + }) + + Method (_CRS) + { + /* Update BAR0 from NVS */ + CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) + BAS0 = \UOB0 + + /* Update BAR1 from NVS */ + CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) + BAS1 = \UOB1 + + Return (^RBUF) + } + + Method (_STA) + { + If (\UOEN == 1) { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl index db82ca9ccea..4026ea28293 100644 --- a/src/soc/intel/baytrail/acpi/pcie.asl +++ b/src/soc/intel/baytrail/acpi/pcie.asl @@ -5,6 +5,31 @@ Device (RP01) { Name (_ADR, 0x001c0000) + Name (_PRW, Package() {9, 3}) + + OperationRegion (PXCS, PCI_Config, 0x40, 0xC0) + Field (PXCS, AnyAcc, NoLock, Preserve) + { + Offset(0x12), + , 13, + LASX, 1, + Offset(0x1A), + ABPX, 1, + , 2, + PDCX, 1, + , 2, + PDSX, 1, + , 1, + Offset(0x20), + , 16, + PSPX, 1, + } + + Device (PXSX) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() {9,3}) + } Method (_PRT) { @@ -27,6 +52,31 @@ Device (RP01) Device (RP02) { Name (_ADR, 0x001c0001) + Name (_PRW, Package() {9, 3}) + + OperationRegion (PXCS, PCI_Config, 0x40, 0xC0) + Field (PXCS, AnyAcc, NoLock, Preserve) + { + Offset(0x12), + , 13, + LASX, 1, + Offset(0x1A), + ABPX, 1, + , 2, + PDCX, 1, + , 2, + PDSX, 1, + , 1, + Offset(0x20), + , 16, + PSPX, 1, + } + + Device (PXSX) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() {9,3}) + } Method (_PRT) { @@ -49,6 +99,31 @@ Device (RP02) Device (RP03) { Name (_ADR, 0x001c0002) + Name (_PRW, Package() {9, 3}) + + OperationRegion (PXCS, PCI_Config, 0x40, 0xC0) + Field (PXCS, AnyAcc, NoLock, Preserve) + { + Offset(0x12), + , 13, + LASX, 1, + Offset(0x1A), + ABPX, 1, + , 2, + PDCX, 1, + , 2, + PDSX, 1, + , 1, + Offset(0x20), + , 16, + PSPX, 1, + } + + Device (PXSX) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() {9,3}) + } Method (_PRT) { @@ -71,6 +146,31 @@ Device (RP03) Device (RP04) { Name (_ADR, 0x001c0003) + Name (_PRW, Package() {9, 3}) + + OperationRegion (PXCS, PCI_Config, 0x40, 0xC0) + Field (PXCS, AnyAcc, NoLock, Preserve) + { + Offset(0x12), + , 13, + LASX, 1, + Offset(0x1A), + ABPX, 1, + , 2, + PDCX, 1, + , 2, + PDSX, 1, + , 1, + Offset(0x20), + , 16, + PSPX, 1, + } + + Device (PXSX) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() {9,3}) + } Method (_PRT) { diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 143327684db..fd19189e523 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -3,6 +3,11 @@ #include #include +#include + +External(\_SB.MPTS, MethodObj) +External(\_SB.MWAK, MethodObj) + /* * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 @@ -10,12 +15,21 @@ Method(_PTS,1) { + If (CondRefOf (\_SB.MPTS)) + { + \_SB.MPTS (Arg0) + } } /* The _WAK method is called on system wakeup */ Method(_WAK,1) { + If (CondRefOf (\_SB.MWAK)) + { + \_SB.MWAK (Arg0) + } + Return(Package(){0,0}) } @@ -24,3 +38,126 @@ Method (_SWS) /* Index into PM1 for device that caused wake */ Return (\PM1I) } + + +OperationRegion (PMIO, SystemIo, ACPI_BASE_ADDRESS, 0x46) +Field (PMIO, ByteAcc, NoLock, Preserve) +{ + , 8, + PWBS, 1, + Offset(0x20), + , 1, + PHPS, 1, + , 1, + PWS0, 1, + , 2, + PWS1, 1, + PWS2, 1, + PWS3, 1, + PEXS, 1, + , 3, + PMEB, 1, + Offset(0x42), + , 1, + GPEC, 1 +} +Field (PMIO, ByteAcc, NoLock, WriteAsZeros) +{ + Offset(0x20), + , 4, + PSCI, 1, + SCIS, 1 +} + +Scope(\_GPE) +{ + + /* Hot Plug SCI */ + Method (_L01) + { + If (\_SB.PCI0.RP01.PDCX) + { + \_SB.PCI0.RP01.PDCX = 1 + Notify (\_SB.PCI0.RP01, 0x00) + } + + If (\_SB.PCI0.RP02.PDCX) + { + \_SB.PCI0.RP02.PDCX = 1 + Notify (\_SB.PCI0.RP02, 0x00) + } + + If (\_SB.PCI0.RP03.PDCX) + { + \_SB.PCI0.RP03.PDCX = 1 + Notify (\_SB.PCI0.RP03, 0x00) + } + + If (\_SB.PCI0.RP04.PDCX) + { + \_SB.PCI0.RP04.PDCX = 1 + Notify (\_SB.PCI0.RP04, 0x00) + } + + PHPS = 1 + } + + Method (_L02) + { + GPEC = 0 + } + + Method (_L04) + { + /* Clear the PUNIT Status Bit. */ + PSCI = 1 + } + + /* PCI Express PME/SCI */ + Method (_L09) + { + If (\_SB.PCI0.RP01.PSPX) + { + \_SB.PCI0.RP01.PSPX = 1 + Notify (\_SB.PCI0.RP01, 0x02) + } + + If (\_SB.PCI0.RP02.PSPX) + { + \_SB.PCI0.RP02.PSPX = 1 + Notify (\_SB.PCI0.RP02, 0x02) + } + + If (\_SB.PCI0.RP03.PSPX) + { + \_SB.PCI0.RP03.PSPX = 1 + Notify (\_SB.PCI0.RP03, 0x02) + } + + If (\_SB.PCI0.RP04.PSPX) + { + \_SB.PCI0.RP04.PSPX = 1 + Notify (\_SB.PCI0.RP04, 0x02) + } + + PEXS = 1 + } + + /* PCI B0 PME */ + Method (_L0D, 0) + { + If (\_SB.PCI0.XHCI.PMES) + { + \_SB.PCI0.XHCI.PMES = 1 + Notify (\_SB.PCI0.XHCI, 0x02) + } + + If (\_SB.PCI0.HDA.PMES) + { + \_SB.PCI0.HDA.PMES = 1 + Notify (\_SB.PCI0.HDA, 0x02) + } + + PMEB = 1 + } +} diff --git a/src/soc/intel/baytrail/acpi/sata.asl b/src/soc/intel/baytrail/acpi/sata.asl new file mode 100644 index 00000000000..bfab9406d6e --- /dev/null +++ b/src/soc/intel/baytrail/acpi/sata.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(SATA) +{ + Name(_ADR,0x00130000) + + OperationRegion (PMEB, PCI_Config, 0x74, 0x04) + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, + , 6, + PMES, 1 + } +} diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl index d11173b9352..055dfdd0815 100644 --- a/src/soc/intel/baytrail/acpi/scc.asl +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -166,3 +166,67 @@ Device (SDCD) PSAT |= 0 } } + +/* SSC devices in PCI mode */ +Device(EM45) +{ + Name(_ADR,0x00170000) + + OperationRegion (PMEB, PCI_Config, 0x84,0x4) + Field (PMEB, WordAcc, NoLock, Preserve) + { + Offset(0x00), + , 8, + PMEE, 1, + , 6, + PMES, 1 + } + + Method (_STA, 0x0, NotSerialized) + { + If (\C0EN == 1) { + Return (0x0) + } Else { + Return (0xF) + } + } + + Device (CARD) + { + /* Slot 0, Function 8 */ + Name (_ADR, 0x8) + + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device(SD11) +{ + Name(_ADR,0x00110000) + + Method (_STA) + { + If (\C1EN == 1) { + Return (0x0) + } Else { + Return (0xF) + } + } +} + +Device(SD12) +{ + Name(_ADR,0x00120000) + + Method (_STA) + { + If (\C2EN == 1) { + Return (0x0) + } Else { + Return (0xF) + } + } +} diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 9f3c76fff15..beb547ce8dd 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -254,9 +254,21 @@ Device (IOSF) /* LPC Bridge 0:1f.0 */ #include "lpc.asl" +/* SATA 0:13.0 */ +#include "sata.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* USB OTG 0:16.0 */ +#include "otg.asl" + +/* TXE 0:1a.0 */ +#include "txe.asl" + +/* HD Audio 0:1b.0 */ +#include "hda.asl" + /* IRQ routing for each PCI device */ #include "irqroute.asl" diff --git a/src/soc/intel/baytrail/acpi/txe.asl b/src/soc/intel/baytrail/acpi/txe.asl new file mode 100644 index 00000000000..3c2dd445802 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/txe.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(SEC0) +{ + Name(_ADR,0x001a0000) + + OperationRegion (PMEB, PCI_Config, 0x84, 0x04) + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, + , 6, + PMES, 1 + } +} diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index 368f34faad7..9daeb5232d7 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -6,15 +6,33 @@ Device (XHCI) Name (_PRW, Package () { 0x0d, 3 }) Name (_S3D, 3) /* Highest D state in S3 state */ + Method(_PSW,1) + { + If (PMES & PMEE) { + PMEE = 0 + PMES = 1 + } + } + + OperationRegion (PMEB, PCI_Config, 0x74, 0x04) + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, + , 6, + PMES, 1 + } + Device (RHUB) { Name (_ADR, 0x00000000) + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + // GPLD: Generate Port Location Data (PLD) Method (GPLD, 1, Serialized) { - Name (PCKG, Package (0x01) { - Buffer (0x10) {} - }) // REV: Revision 0x02 for ACPI 5.0 CreateField (DerefOf (PCKG[0]), 0, 0x07, REV) diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 412762cdd08..0de380efd28 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -53,6 +53,7 @@ struct soc_intel_baytrail_config { int lpss_acpi_mode; int scc_acpi_mode; int lpe_acpi_mode; + int otg_acpi_mode; /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 3e83bcc0883..557fc00fc91 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -50,12 +50,12 @@ unsigned int smbios_processor_family(struct cpuid_result res) /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0x17000f), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), + REG_MSR_OR(MSR_POWER_MISC, ENABLE_ULFM_AUTOCM_MASK | ENABLE_IA_UNTRUSTED_MODE), REG_SCRIPT_END }; diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index 46fd9cc6eaf..540d658e4a1 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -29,16 +29,19 @@ struct __packed device_nvs { u8 lpss_en[14]; u8 scc_en[3]; u8 lpe_en; + u8 otg_en; /* BAR 0 */ u32 lpss_bar0[14]; u32 scc_bar0[3]; u32 lpe_bar0; + u32 otg_bar0; /* BAR 1 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1; + u32 otg_bar1; /* Extra */ u32 lpe_fw; /* LPE Firmware */ diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 7938509b97d..3beccf47262 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -104,7 +104,7 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_PORT_SCORE 0x48 /* SCORE */ #define IOSF_PORT_0x55 0x55 #define IOSF_PORT_0x58 0x58 -#define IOSF_PORT_0x59 0x59 +#define IOSF_PORT_OTG 0x59 #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ @@ -148,8 +148,8 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) #define IOSF_OP_READ_0x58 0x06 #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) +#define IOSF_OP_READ_OTG 0x06 +#define IOSF_OP_WRITE_OTG (IOSF_OP_READ_OTG | 1) #define IOSF_OP_READ_0x5a 0x04 #define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) #define IOSF_OP_READ_USHPHY 0x06 @@ -336,6 +336,18 @@ void iosf_ssus_write(int reg, uint32_t val); #define USHPHY_REE_DAC_CONTROL 0x80b8 #define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 +/* + * OTG Registers + */ + +#define OTG_PCICFGCTR1 0x500 +# define OTG_PCICFGCTR1_INT_PIN_MASK (0xf << 8) +# define OTG_PCICFGCTR1_INT_PIN_SHIFT 8 +# define OTG_PCICFGCTR1_BAR1_DIS (1 << 7) +# define OTG_PCICFGCTR1_PME_SUPPORT 0x7C +# define OTG_PCICFGCTR1_ACPI_INT_EN (1 << 1) +# define OTG_PCICFGCTR1_PCI_CFG_DIS (1 << 0) + /* * LPE Registers */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 2e6b551ee65..2779f179eac 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -10,6 +10,7 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define ENABLE_IA_UNTRUSTED_MODE (1 << 6) #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 21060eee1a6..66598eb9f06 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -230,12 +230,12 @@ void iosf_port58_write(int reg, uint32_t val) uint32_t iosf_port59_read(int reg) { - return iosf_read_port(IOSF_READ(0x59), reg); + return iosf_read_port(IOSF_READ(OTG), reg); } void iosf_port59_write(int reg, uint32_t val) { - iosf_write_port(IOSF_WRITE(0x59), reg, val); + iosf_write_port(IOSF_WRITE(OTG), reg, val); } uint32_t iosf_port5a_read(int reg) diff --git a/src/soc/intel/baytrail/otg.c b/src/soc/intel/baytrail/otg.c new file mode 100644 index 00000000000..0d1f33cac2b --- /dev/null +++ b/src/soc/intel/baytrail/otg.c @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +const struct reg_script otg_power_save[] = { + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 4), /* vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en */ + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 0), /* vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en */ + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 5), /* vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en */ + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 3), /* vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en */ + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 1), /* vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en */ + REG_IOSF_OR(IOSF_PORT_OTG, 0x1e0, 1 << 2), /* vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en */ + REG_SCRIPT_END +}; + +const struct reg_script configure_usb_ulpi[] = { + /* USB_ULPI_0_CLK */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x338, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x330, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA0 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x388, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x380, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA1 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x368, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x360, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA2 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x318, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x310, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA3 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x378, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x370, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA4 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x308, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x300, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA5 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x398, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x390, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA6 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x328, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x320, ~(0x187), (0x101)), + /* USB_ULPI_0_DATA7 */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x3a8, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x3a0, ~(0x187), (0x101)), + /* USB_ULPI_0_DIR */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x348, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x340, ~(0x187), (0x81)), + /* USB_ULPI_0_NXT */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x358, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x350, ~(0x187), (0x101)), + /* USB_ULPI_0_STP */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x3b8, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x3b0, ~(0x187), (0x81)), + /* USB_ULPI_0_REFCLK */ + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x288, ~(0x7), (0x2)), + REG_MMIO_RMW32(GPSSUS_PAD_BASE + 0x280, ~(0x187), (0x101)) +}; + +const struct reg_script otg_init_script[] = { + REG_SCRIPT_NEXT(configure_usb_ulpi), + /* Disable USB_ULPI_REFCLK */ + REG_PCI_OR32(0xa0, 1 << 17), + /* VCO calibration code starting point = 0xa */ + REG_RES_RMW16(PCI_BASE_ADDRESS_0, 0x1000ac, ~0x1f, 0xa), + /* PLL_VCO_calibration_trim_code = 7 */ + REG_RES_RMW16(PCI_BASE_ADDRESS_0, 0x100784, ~(7 << 4), 7 << 4), + /* vlv.usb.xdci_otg.usb3_cadence.otg3_phy.u1_power_state_definition.tx_en = 1 */ + REG_RES_OR16(PCI_BASE_ADDRESS_0, 0x100004, 1 << 2), + /* Configure INTA for PCI mode */ + REG_IOSF_RMW(IOSF_PORT_OTG, OTG_PCICFGCTR1, + ~OTG_PCICFGCTR1_INT_PIN_MASK, (INTA << OTG_PCICFGCTR1_INT_PIN_SHIFT)), + REG_SCRIPT_END +}; + +static void store_acpi_nvs(struct device *dev) +{ + struct resource *bar; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + dev_nvs->otg_bar0 = (u32)bar->base; + + bar = probe_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + dev_nvs->otg_bar1 = (u32)bar->base; +} + +static void otg_enable_acpi_mode(struct device *dev) +{ + struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR16(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_OTG, OTG_PCICFGCTR1, + OTG_PCICFGCTR1_PCI_CFG_DIS | OTG_PCICFGCTR1_ACPI_INT_EN), + + REG_SCRIPT_END + }; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + store_acpi_nvs(dev); + + /* Device is enabled in ACPI mode */ + dev_nvs->otg_en = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} + +static void otg_init(struct device *dev) +{ + struct soc_intel_baytrail_config *config = config_of(dev); + + /* Configure OTG device */ + reg_script_run_on_dev(dev, otg_init_script); + + if (config->otg_acpi_mode) + otg_enable_acpi_mode(dev); + else + store_acpi_nvs(dev); +} + +static void otg_final(struct device *dev) +{ + /* + * S0ix PnP setting for OTG. Was in perf_power_settings, but + * the IOSF writes hang the platform when OTG is disabled. + */ + reg_script_run_on_dev(dev, otg_power_save); +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = otg_init, + .final = otg_final, + .enable = southcluster_enable_dev, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VID_INTEL, + .device = OTG_DEVID +}; diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 8783e1fde92..8420f5637d9 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -212,12 +212,6 @@ E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_o E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on -E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en -E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en -E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en -E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index be058d013b2..81e8e1ab4e6 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -27,6 +27,7 @@ void punit_init(void) reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + reg |= (1 << 6); /* Configure VR low power mode for C0 and above. */ if (rid >= RID_C_STEPPING_START && cfg != NULL && (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) {