[InstCombine] Combine extract from get_active_lane_mask where all lanes inactive (llvm#183329)

When extracting a subvector from the result of a get_active_lane_mask, return
a constant zero vector if it can be proven that all lanes will be inactive.

For example, the result of the extract below will be a subvector where
every lane is inactive if X & Y are const, and `Y * VScale >= X`:
  vector.extract(get.active.lane.mask(Start, X), Y)

Author: kmclaughlin-arm

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

@@ -3927,6 +3927,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
         return replaceOperand(CI, 0, InsertTuple);
     }
 
+    ConstantInt *ALMUpperBound;
+    if (match(Vec, m_Intrinsic<Intrinsic::get_active_lane_mask>(
+                       m_Value(), m_ConstantInt(ALMUpperBound)))) {
+      const auto &Attrs = II->getFunction()->getAttributes().getFnAttrs();
+      unsigned VScaleMin = Attrs.getVScaleRangeMin();
+      if (ExtractIdx * VScaleMin >= ALMUpperBound->getZExtValue())
+        return replaceInstUsesWith(CI,
+                                   ConstantVector::getNullValue(ReturnType));
+    }
+
     auto *DstTy = dyn_cast<VectorType>(ReturnType);
     auto *VecTy = dyn_cast<VectorType>(Vec->getType());
 

llvm/test/Transforms/InstCombine/get_active_lane_mask.ll

@@ -36,3 +36,43 @@ define <vscale x 4 x i1> @bail_lhs_is_zero() {
   %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
   ret <vscale x 4 x i1> %mask
 }
+
+define <4 x i1> @remove_all_false_subvector() {
+; CHECK-LABEL: define <4 x i1> @remove_all_false_subvector() {
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
+;
+  %wide.alm = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i32 0, i32 7)
+  %ext = tail call <4 x i1> @llvm.vector.extract.v4i1.nxv16i1(<vscale x 16 x i1> %wide.alm, i64 8)
+  ret <4 x i1> %ext
+}
+
+define <vscale x 4 x i1> @remove_all_false_subvector_vscale() vscale_range(2,16) {
+; CHECK-LABEL: define <vscale x 4 x i1> @remove_all_false_subvector_vscale(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    ret <vscale x 4 x i1> zeroinitializer
+;
+  %wide.alm = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 7)
+  %ext = tail call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %wide.alm, i64 4)
+  ret <vscale x 4 x i1> %ext
+}
+
+define <vscale x 2 x i1> @active_lane_mask_non_const_start(i64 %start) {
+; CHECK-LABEL: define <vscale x 2 x i1> @active_lane_mask_non_const_start(
+; CHECK-SAME: i64 [[START:%.*]]) {
+; CHECK-NEXT:    ret <vscale x 2 x i1> zeroinitializer
+;
+  %wide.alm = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %start, i64 1)
+  %ext = tail call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv4i1(<vscale x 4 x i1> %wide.alm, i64 2)
+  ret <vscale x 2 x i1> %ext
+}
+
+define <4 x i1> @ext_has_active_lanes() {
+; CHECK-LABEL: define <4 x i1> @ext_has_active_lanes() {
+; CHECK-NEXT:    [[WIDE_ALM:%.*]] = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 0, i32 7)
+; CHECK-NEXT:    [[EXT:%.*]] = tail call <4 x i1> @llvm.vector.extract.v4i1.nxv16i1(<vscale x 16 x i1> [[WIDE_ALM]], i64 4)
+; CHECK-NEXT:    ret <4 x i1> [[EXT]]
+;
+  %wide.alm = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i32 0, i32 7)
+  %ext = tail call <4 x i1> @llvm.vector.extract.v4i1.nxv16i1(<vscale x 16 x i1> %wide.alm, i64 4)
+  ret <4 x i1> %ext
+}