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i#3544 RV64: Rebase the dcontext pointer. (#7235)
For RISC-V the dcontext_t struct is larger than the biggest valid displacement of the load and store instructions. By rebasing the pointer kept in spill_state_t's TLS slot by 0x800, we can access the entire struct, because the displacement can be in the range of -0x800 to 0x7ff. Architectures other than RV64 are unaffected by these changes. Issue: #3544
1 parent e7b57f6 commit cc7830f

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8 files changed

+132
-44
lines changed

8 files changed

+132
-44
lines changed

‎core/arch/arch_exports.h

+30
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/* **********************************************************
22
* Copyright (c) 2011-2022 Google, Inc. All rights reserved.
33
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
4+
* Copyright (c) 2025 Foundation of Research and Technology, Hellas.
45
* **********************************************************/
56

67
/*
@@ -165,6 +166,10 @@ typedef struct _spill_state_t {
165166
reg_t reg_stolen;
166167
#endif
167168
/* XXX: move this below the tables to fit more on cache line */
169+
/* In RISCV64 dcontext does not poiont to the actual dcontext. It points somewhere
170+
* in the middle of that. This value is the actual pointer offseted by
171+
* DCONTEXT_TLS_MIDPTR_OFFSET.
172+
*/
168173
dcontext_t *dcontext;
169174
#if defined(RISCV64) || defined(AARCHXX)
170175
/* We store addresses here so we can load pointer-sized addresses into
@@ -1819,4 +1824,29 @@ typedef struct _rseq_entry_state_t {
18191824
} rseq_entry_state_t;
18201825
#endif
18211826

1827+
/*
1828+
* In riscv we cannot address the entire dcontext by using base + immediate.
1829+
* For the reason we add 0x800 to the saved pointer and access it by
1830+
* substracting 0x800 from the offset in the struct.
1831+
*/
1832+
#ifdef RISCV64
1833+
# define DCONTEXT_TLS_MIDPTR_OFFSET 0x800
1834+
#else
1835+
# define DCONTEXT_TLS_MIDPTR_OFFSET 0
1836+
#endif
1837+
1838+
#if (DCONTEXT_TLS_MIDPTR_OFFSET != 0)
1839+
# define DCONTEXT_ACTUAL_TO_TLS_PTR(x) \
1840+
((dcontext_t *)(((ptr_uint_t)x) + DCONTEXT_TLS_MIDPTR_OFFSET))
1841+
# define DCONTEXT_TLS_TO_ACTUAL_PTR(x) \
1842+
((dcontext_t *)(((ptr_uint_t)x) - DCONTEXT_TLS_MIDPTR_OFFSET))
1843+
# define DCONTEXT_ACTUAL_TO_TLS_OFFSET(x) (x - DCONTEXT_TLS_MIDPTR_OFFSET)
1844+
# define DCONTEXT_TLS_TO_ACTUAL_OFFSET(x) (x + DCONTEXT_TLS_MIDPTR_OFFSET)
1845+
#else
1846+
# define DCONTEXT_ACTUAL_TO_TLS_PTR(x) x
1847+
# define DCONTEXT_TLS_TO_ACTUAL_PTR(x) x
1848+
# define DCONTEXT_ACTUAL_TO_TLS_OFFSET(x) x
1849+
# define DCONTEXT_TLS_TO_ACTUAL_OFFSET(x) x
1850+
#endif
1851+
18221852
#endif /* _ARCH_EXPORTS_H_ */

‎core/arch/emit_utils_shared.c

+31-4
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/* **********************************************************
22
* Copyright (c) 2010-2022 Google, Inc. All rights reserved.
33
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
4+
* Copyright (c) 2025 Foundation of Research and Technology, Hellas.
45
* **********************************************************/
56

67
/*
@@ -2180,12 +2181,16 @@ emit_fcache_enter_common(dcontext_t *dcontext, generated_code_t *code, byte *pc,
21802181
#elif defined(RISCV64)
21812182
APP(&ilist,
21822183
INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_A0),
2183-
opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
2184-
REG_OFFSET(DR_REG_A0), OPSZ_8)));
2184+
opnd_create_base_disp(
2185+
REG_DCXT, DR_REG_NULL, 0,
2186+
DCONTEXT_ACTUAL_TO_TLS_OFFSET((int)REG_OFFSET(DR_REG_A0)),
2187+
OPSZ_8)));
21852188
APP(&ilist,
21862189
INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_A1),
2187-
opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
2188-
REG_OFFSET(DR_REG_A1), OPSZ_8)));
2190+
opnd_create_base_disp(
2191+
REG_DCXT, DR_REG_NULL, 0,
2192+
DCONTEXT_ACTUAL_TO_TLS_OFFSET((int)REG_OFFSET(DR_REG_A1)),
2193+
OPSZ_8)));
21892194

21902195
APP(&ilist,
21912196
INSTR_CREATE_sd(
@@ -2380,9 +2385,31 @@ append_call_dispatch(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
23802385
/* call central d_r_dispatch routine */
23812386
/* for x64 linux we could optimize and avoid the "mov rdi, rdi" */
23822387
/* for ARM we use _noreturn to avoid storing to %lr */
2388+
2389+
/*
2390+
* REG_DCTXT holds the rebased dcontext d_r_dispatch expects the normal one
2391+
* so we should restore it.
2392+
*
2393+
* Currently only affects RISCV64
2394+
*/
2395+
#if (DCONTEXT_TLS_MIDPTR_OFFSET != 0)
2396+
if (absolute) {
2397+
dr_insert_call_noreturn((void *)dcontext, ilist, NULL /*append*/,
2398+
(void *)d_r_dispatch, 1,
2399+
OPND_CREATE_INTPTR((ptr_int_t)dcontext));
2400+
} else {
2401+
APP(ilist,
2402+
XINST_CREATE_add_2src(dcontext, opnd_create_reg(DR_REG_A0),
2403+
opnd_create_reg(REG_DCTXT),
2404+
OPND_CREATE_INT32(-DCONTEXT_TLS_MIDPTR_OFFSET)));
2405+
dr_insert_call_noreturn((void *)dcontext, ilist, NULL /*append*/,
2406+
(void *)d_r_dispatch, 1, opnd_create_reg(DR_REG_A0));
2407+
}
2408+
#else
23832409
dr_insert_call_noreturn(
23842410
(void *)dcontext, ilist, NULL /*append*/, (void *)d_r_dispatch, 1,
23852411
absolute ? OPND_CREATE_INTPTR((ptr_int_t)dcontext) : opnd_create_reg(REG_DCTXT));
2412+
#endif
23862413

23872414
/* d_r_dispatch() shouldn't return! */
23882415
insert_reachable_cti(dcontext, ilist, NULL, vmcode_get_start(),

‎core/arch/mangle_shared.c

+20-8
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
* Copyright (c) 2010-2022 Google, Inc. All rights reserved.
33
* Copyright (c) 2010 Massachusetts Institute of Technology All rights reserved.
44
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
5+
* Copyright (c) 2025 Foundation of Research and Technology, Hellas.
56
* ******************************************************************************/
67

78
/*
@@ -81,6 +82,12 @@ get_clean_call_temp_stack_size(void)
8182
/* utility routines for inserting clean calls to an instrumentation routine
8283
* strategy is very similar to fcache_enter/return
8384
* FIXME: try to share code with fcache_enter/return?
85+
* TODO i#3544: Return the correct mcontext base when DCONTEXT_TLS_MIDPTR_OFFSET is used.
86+
* This will need calls like opnd_create_dcontext_field_via_reg_sz to be replaced
87+
* with something else. Currently we work around that by assuming that we have the
88+
* dcontext pointer (offseted) instead of the mcontext when DCONTEXT_TLS_MIDPTR_OFFSET is
89+
* not zero. For that reason we substract DCONTEXT_TLS_MIDPTR_OFFSET in the offsets
90+
* created at emit_fcache_enter_common().
8491
*
8592
* first swap stacks to DynamoRIO stack:
8693
* SAVE_TO_UPCONTEXT %xsp,xsp_OFFSET
@@ -757,8 +764,9 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
757764
* We save it to dcontext.mcontext.x0.
758765
*/
759766
PRE(ilist, instr,
760-
XINST_CREATE_store(dcontext, OPND_CREATE_MEMPTR(link_reg, 0),
761-
opnd_create_reg(SCRATCH_REG0)));
767+
XINST_CREATE_store(
768+
dcontext, OPND_CREATE_MEMPTR(link_reg, -DCONTEXT_TLS_MIDPTR_OFFSET),
769+
opnd_create_reg(SCRATCH_REG0)));
762770
instrlist_insert_mov_immed_ptrsz(dcontext, (ptr_int_t)DR_WHERE_CLEAN_CALLEE,
763771
opnd_create_reg(SCRATCH_REG0), ilist, instr,
764772
NULL, NULL);
@@ -769,8 +777,9 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
769777
WHEREAMI_OFFSET));
770778
/* Restore scratch_reg from dcontext.mcontext.x0. */
771779
PRE(ilist, instr,
772-
XINST_CREATE_load(dcontext, opnd_create_reg(SCRATCH_REG0),
773-
OPND_CREATE_MEMPTR(link_reg, 0)));
780+
XINST_CREATE_load(
781+
dcontext, opnd_create_reg(SCRATCH_REG0),
782+
OPND_CREATE_MEMPTR(link_reg, -DCONTEXT_TLS_MIDPTR_OFFSET)));
774783
#else
775784
/* SCRATCH_REG0 is dead here, because clean calls only support "cdecl",
776785
* which specifies that the caller must save xax (and xcx and xdx).
@@ -823,8 +832,10 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
823832
* We save it to dcontext.mcontext.x0.
824833
*/
825834
PRE(ilist, instr,
826-
XINST_CREATE_store(dcontext, OPND_CREATE_MEMPTR(SCRATCH_REG0, 0),
827-
opnd_create_reg(SCRATCH_REG1)));
835+
XINST_CREATE_store(
836+
dcontext,
837+
OPND_CREATE_MEMPTR(SCRATCH_REG0, -DCONTEXT_TLS_MIDPTR_OFFSET),
838+
opnd_create_reg(SCRATCH_REG1)));
828839
instrlist_insert_mov_immed_ptrsz(dcontext, (ptr_int_t)whereami,
829840
opnd_create_reg(SCRATCH_REG1), ilist, instr,
830841
NULL, NULL);
@@ -835,8 +846,9 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
835846
WHEREAMI_OFFSET));
836847
/* Restore scratch_reg from dcontext.mcontext.x0. */
837848
PRE(ilist, instr,
838-
XINST_CREATE_load(dcontext, opnd_create_reg(SCRATCH_REG1),
839-
OPND_CREATE_MEMPTR(SCRATCH_REG0, 0)));
849+
XINST_CREATE_load(
850+
dcontext, opnd_create_reg(SCRATCH_REG1),
851+
OPND_CREATE_MEMPTR(SCRATCH_REG0, -DCONTEXT_TLS_MIDPTR_OFFSET)));
840852
#else
841853
PRE(ilist, instr,
842854
instr_create_save_immed_to_dc_via_reg(dcontext, SCRATCH_REG0,

‎core/arch/riscv64/emit_utils.c

+15-13
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* **********************************************************
22
* Copyright (c) 2022 Rivos, Inc. All rights reserved.
3-
* Copyright (c) 2024 Foundation of Research and Technology, Hellas.
3+
* Copyright (c) 2024-2025 Foundation of Research and Technology, Hellas.
44
* **********************************************************/
55

66
/*
@@ -691,19 +691,20 @@ append_restore_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
691691
}
692692

693693
if (proc_has_feature(FEATURE_VECTOR)) {
694+
APP(ilist,
695+
INSTR_CREATE_addi(
696+
dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
697+
opnd_create_immed_int(
698+
DCONTEXT_ACTUAL_TO_TLS_OFFSET(VREG_OFFSET(DR_REG_VR0)), OPSZ_12b)));
699+
memopnd = opnd_create_base_disp(DR_REG_A1, REG_NULL, 0, 0,
700+
reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
694701
/* ma: mask agnostic
695702
* ta: tail agnostic
696703
* sew: selected element width
697704
* lmul: vector register group multiplier
698705
*
699706
* ma ta sew=8 lmul=8 */
700707
vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
701-
memopnd = opnd_create_dcontext_field_via_reg_sz(
702-
dcontext, DR_REG_A1, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
703-
APP(ilist,
704-
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A1),
705-
opnd_create_reg(REG_DCXT),
706-
opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0), OPSZ_12b)));
707708
/* For the following vector instructions, set the element width to 8b, and use 8
708709
* registers as a group (lmul=8).
709710
*/
@@ -828,19 +829,20 @@ append_save_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
828829
}
829830

830831
if (proc_has_feature(FEATURE_VECTOR)) {
832+
APP(ilist,
833+
INSTR_CREATE_addi(
834+
dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
835+
opnd_create_immed_int(
836+
DCONTEXT_ACTUAL_TO_TLS_OFFSET(VREG_OFFSET(DR_REG_VR0)), OPSZ_12b)));
837+
memopnd = opnd_create_base_disp(DR_REG_A1, REG_NULL, 0, 0,
838+
reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
831839
/* ma: mask agnostic
832840
* ta: tail agnostic
833841
* sew: selected element width
834842
* lmul: vector register group multiplier
835843
*
836844
* ma ta sew=8 lmul=8 */
837845
vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
838-
memopnd = opnd_create_dcontext_field_via_reg_sz(
839-
dcontext, DR_REG_A1, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
840-
APP(ilist,
841-
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A1),
842-
opnd_create_reg(REG_DCXT),
843-
opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0), OPSZ_12b)));
844846
/* For the following vector instructions, set the element width to 8b, and use 8
845847
* registers as a group (lmul=8).
846848
*/

‎core/arch/riscv64/mangle.c

+13-13
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* **********************************************************
22
* Copyright (c) 2022 Rivos, Inc. All rights reserved.
3-
* Copyright (c) 2024 Foundation of Research and Technology, Hellas.
3+
* Copyright (c) 2024-2025 Foundation of Research and Technology, Hellas.
44
* **********************************************************/
55

66
/*
@@ -223,19 +223,19 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
223223

224224
/* Push vector registers. */
225225
if (proc_has_feature(FEATURE_VECTOR)) {
226+
PRE(ilist, instr,
227+
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
228+
opnd_create_reg(DR_REG_SP),
229+
opnd_create_immed_int(dstack_offs, OPSZ_12b)));
230+
memopnd = opnd_create_base_disp(DR_REG_A0, REG_NULL, 0, 0,
231+
reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
226232
/* ma: mask agnostic
227233
* ta: tail agnostic
228234
* sew: selected element width
229235
* lmul: vector register group multiplier
230236
*
231237
* ma ta sew=8 lmul=8 */
232238
vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
233-
memopnd = opnd_create_dcontext_field_via_reg_sz(
234-
dcontext, DR_REG_A0, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
235-
PRE(ilist, instr,
236-
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
237-
opnd_create_reg(DR_REG_SP),
238-
opnd_create_immed_int(dstack_offs, OPSZ_12b)));
239239
/* For the following vector instructions, set the element width to 8b, and use 8
240240
* registers as a group (lmul=8).
241241
*/
@@ -294,19 +294,19 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
294294
/* Pop vector registers. */
295295
current_offs -= proc_num_simd_registers() * sizeof(dr_simd_t);
296296
if (proc_has_feature(FEATURE_VECTOR)) {
297+
PRE(ilist, instr,
298+
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
299+
opnd_create_reg(DR_REG_SP),
300+
opnd_create_immed_int(current_offs, OPSZ_12b)));
301+
memopnd = opnd_create_base_disp(DR_REG_A0, REG_NULL, 0, 0,
302+
reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
297303
/* ma: mask agnostic
298304
* ta: tail agnostic
299305
* sew: selected element width
300306
* lmul: vector register group multiplier
301307
*
302308
* ma ta sew=8 lmul=8 */
303309
vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
304-
memopnd = opnd_create_dcontext_field_via_reg_sz(
305-
dcontext, DR_REG_A0, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
306-
PRE(ilist, instr,
307-
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
308-
opnd_create_reg(DR_REG_SP),
309-
opnd_create_immed_int(current_offs, OPSZ_12b)));
310310
/* For the following vector instructions, set the element width to 8b, and use 8
311311
* registers as a group (lmul=8).
312312
*/

‎core/dispatch.c

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/* **********************************************************
22
* Copyright (c) 2011-2023 Google, Inc. All rights reserved.
33
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
4+
* Copyright (c) 2025 Foundation of Research and Technology, Hellas.
45
* **********************************************************/
56

67
/*
@@ -569,7 +570,8 @@ enter_fcache(dcontext_t *dcontext, fcache_enter_func_t entry, cache_pc pc)
569570
* paths were missed?
570571
*/
571572
PTHREAD_JIT_READ();
572-
(*entry)(dcontext);
573+
574+
(*entry)(DCONTEXT_ACTUAL_TO_TLS_PTR(dcontext));
573575
IF_WINDOWS(ASSERT_NOT_REACHED()); /* returns for signals on unix */
574576
}
575577

‎core/ir/opnd_shared.c

+7-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/* **********************************************************
22
* Copyright (c) 2011-2022 Google, Inc. All rights reserved.
33
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
4+
* Copyright (c) 2025 Foundation of Research and Technology, Hellas.
45
* **********************************************************/
56

67
/*
@@ -2898,14 +2899,16 @@ dcontext_opnd_common(dcontext_t *dcontext, bool absolute, reg_id_t basereg, int
28982899
absolute ? REG_NULL : (basereg == REG_NULL ? REG_DCXT_PROT : basereg),
28992900
REG_NULL, 0,
29002901
((int)(ptr_int_t)(absolute ? dcontext->upcontext.separate_upcontext : 0)) +
2901-
offs,
2902+
DCONTEXT_ACTUAL_TO_TLS_OFFSET(offs),
29022903
size);
29032904
} else {
29042905
if (offs >= sizeof(unprotected_context_t))
29052906
offs -= sizeof(unprotected_context_t);
29062907
return opnd_create_base_disp(
29072908
absolute ? REG_NULL : (basereg == REG_NULL ? REG_DCXT : basereg), REG_NULL, 0,
2908-
((int)(ptr_int_t)(absolute ? dcontext : 0)) + offs, size);
2909+
((int)(ptr_int_t)(absolute ? dcontext : 0)) +
2910+
DCONTEXT_ACTUAL_TO_TLS_OFFSET(offs),
2911+
size);
29092912
}
29102913
}
29112914

@@ -2950,7 +2953,8 @@ update_dcontext_address(opnd_t op, dcontext_t *old_dcontext, dcontext_t *new_dco
29502953
opnd_get_index(op) == REG_NULL,
29512954
"update_dcontext_address: invalid opnd");
29522955
IF_X64(ASSERT_NOT_IMPLEMENTED(false));
2953-
offs = opnd_get_disp(op) - (uint)(ptr_uint_t)old_dcontext;
2956+
offs =
2957+
opnd_get_disp(op) - (uint)(ptr_uint_t)old_dcontext + DCONTEXT_TLS_MIDPTR_OFFSET;
29542958
if (offs >= 0 && offs < sizeof(dcontext_t)) {
29552959
/* don't pass raw offset, add in upcontext size */
29562960
offs += sizeof(unprotected_context_t);

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