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DE1_TOP.map.rpt
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Analysis & Synthesis report for DE1_TOP
Tue Jun 19 02:41:48 2018
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Parallel Compilation
6. Analysis & Synthesis Source Files Read
7. Analysis & Synthesis Resource Usage Summary
8. Analysis & Synthesis Resource Utilization by Entity
9. Analysis & Synthesis RAM Summary
10. Analysis & Synthesis IP Cores Summary
11. State Machine - |DE1_TOP|keyboard:keyboard_inst|state
12. State Machine - |DE1_TOP|cpu68:cpu68_inst|state
13. Registers Protected by Synthesis
14. Registers Removed During Synthesis
15. Removed Registers Triggering Further Register Optimizations
16. General Register Statistics
17. Inverted Register Statistics
18. Multiplexer Restructuring Statistics (Restructuring Performed)
19. Source assignments for Top-level Entity: |DE1_TOP
20. Source assignments for rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|altsyncram_cpc2:altsyncram1
21. Source assignments for internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|altsyncram_bob2:altsyncram1
22. Source assignments for ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1
23. Source assignments for OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component|altsyncram_8681:auto_generated
24. Source assignments for OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component|altsyncram_vrr1:auto_generated
25. Parameter Settings for User Entity Instance: Top-level Entity: |DE1_TOP
26. Parameter Settings for User Entity Instance: rom:rom_inst|altsyncram:altsyncram_component
27. Parameter Settings for User Entity Instance: internal_ram:internal_ram_inst|altsyncram:altsyncram_component
28. Parameter Settings for User Entity Instance: ram:ram_inst|altsyncram:altsyncram_component
29. Parameter Settings for User Entity Instance: async_receiver:async_receiver_inst
30. Parameter Settings for User Entity Instance: async_transmitter:async_transmitter_inst
31. Parameter Settings for User Entity Instance: PLL:PLL_inst|altpll:altpll_component
32. Parameter Settings for User Entity Instance: top_sync_vg_pattern:top_sync_vg_pattern_inst
33. Parameter Settings for User Entity Instance: top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg
34. Parameter Settings for User Entity Instance: top_sync_vg_pattern:top_sync_vg_pattern_inst|pattern_vg:pattern_vg
35. Parameter Settings for User Entity Instance: OSD:OSD_inst
36. Parameter Settings for User Entity Instance: OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component
37. Parameter Settings for User Entity Instance: OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component
38. Parameter Settings for User Entity Instance: keyboard:keyboard_inst
39. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
40. altsyncram Parameter Settings by Entity Instance
41. altpll Parameter Settings by Entity Instance
42. Port Connectivity Checks: "keyboard:keyboard_inst"
43. Port Connectivity Checks: "OSD:OSD_inst"
44. Port Connectivity Checks: "top_sync_vg_pattern:top_sync_vg_pattern_inst|pattern_vg:pattern_vg"
45. Port Connectivity Checks: "top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg"
46. Port Connectivity Checks: "top_sync_vg_pattern:top_sync_vg_pattern_inst"
47. Port Connectivity Checks: "async_transmitter:async_transmitter_inst"
48. Port Connectivity Checks: "async_receiver:async_receiver_inst"
49. Port Connectivity Checks: "cpu68:cpu68_inst"
50. SignalTap II Logic Analyzer Settings
51. In-System Memory Content Editor Settings
52. Elapsed Time Per Partition
53. Connections to In-System Debugging Instance "auto_signaltap_0"
54. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jun 19 02:41:47 2018 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; DE1_TOP ;
; Top-level Entity Name ; DE1_TOP ;
; Family ; Cyclone II ;
; Total logic elements ; 5,270 ;
; Total combinational functions ; 3,442 ;
; Dedicated logic registers ; 2,986 ;
; Total registers ; 2986 ;
; Total pins ; 283 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 126,976 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
+------------------------------------+-------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C20F484C7 ; ;
; Top-level entity name ; DE1_TOP ; DE1_TOP ;
; Family name ; Cyclone II ; Stratix ;
; Maximum processors allowed for parallel compilation ; All ; ;
; VHDL Show LMF Mapping Messages ; Off ; ;
; Verilog Show LMF Mapping Messages ; Off ; ;
; VHDL Version ; VHDL_2008 ; VHDL_1993 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; -1 ; -1 ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name ; Setting ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; "VERIFIED_SAFE" ;
+----------------------+--------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.0% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------------+---------+
; System68/cpu68.vhd ; yes ; User VHDL File ; D:/Electronics/MPU401 Core DE1/System68/cpu68.vhd ; ;
; keyboard.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/keyboard.v ; ;
; async_transmitter.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/async_transmitter.v ; ;
; async_receiver.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/async_receiver.v ; ;
; top_sync_vg_pattern.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/top_sync_vg_pattern.v ; ;
; sync_vg.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/sync_vg.v ; ;
; pattern_vg.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/pattern_vg.v ; ;
; osd.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/osd.v ; ;
; font_rom.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/font_rom.v ; ;
; char_ram.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/char_ram.v ; ;
; SEG7_LUT_4.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/SEG7_LUT_4.v ; ;
; SEG7_LUT.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/SEG7_LUT.v ; ;
; DE1_TOP.v ; yes ; User Verilog HDL File ; D:/Electronics/MPU401 Core DE1/DE1_TOP.v ; ;
; PLL.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/PLL.v ; ;
; rom.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/rom.v ; ;
; ram.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/ram.v ; ;
; internal_ram.v ; yes ; User Wizard-Generated File ; D:/Electronics/MPU401 Core DE1/internal_ram.v ; ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_9ed1.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_9ed1.tdf ; ;
; db/altsyncram_cpc2.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_cpc2.tdf ; ;
; 6801v0b55p.mif ; yes ; Auto-Found Memory Initialization File ; D:/Electronics/MPU401 Core DE1/6801v0b55p.mif ; ;
; sld_mod_ram_rom.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd ; ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ;
; db/altsyncram_8eg1.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_8eg1.tdf ; ;
; db/altsyncram_bob2.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_bob2.tdf ; ;
; db/altsyncram_9dg1.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_9dg1.tdf ; ;
; db/altsyncram_7ub2.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_7ub2.tdf ; ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf ; ;
; stratix_pll.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/altsyncram_8681.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_8681.tdf ; ;
; fontromdata.mif ; yes ; Auto-Found Memory Initialization File ; D:/Electronics/MPU401 Core DE1/fontromdata.mif ; ;
; db/altsyncram_vrr1.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_vrr1.tdf ; ;
; sld_signaltap.vhd ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap.vhd ; ;
; sld_signaltap_impl.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd ; ;
; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_ela_control.vhd ; ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ;
; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_mbpmg.vhd ; ;
; sld_ela_trigger_flow_mgr.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd ; ;
; sld_buffer_manager.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd ; ;
; sld_gap_detector.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_gap_detector.vhd ; ;
; db/altsyncram_ne54.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/altsyncram_ne54.tdf ; ;
; altdpram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.tdf ; ;
; memmodes.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/memmodes.inc ; ;
; a_hdffe.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_hdffe.inc ; ;
; alt_le_rden_reg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_le_rden_reg.inc ; ;
; altsyncram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.inc ; ;
; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf ; ;
; muxlut.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muxlut.inc ; ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc ; ;
; altshift.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc ; ;
; db/mux_eoc.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/mux_eoc.tdf ; ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.tdf ; ;
; declut.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/declut.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; db/decode_rqf.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/decode_rqf.tdf ; ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
; db/cntr_mdi.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cntr_mdi.tdf ; ;
; db/cmpr_bcc.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cmpr_bcc.tdf ; ;
; db/cntr_v1j.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cntr_v1j.tdf ; ;
; db/cntr_1ci.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cntr_1ci.tdf ; ;
; db/cmpr_9cc.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cmpr_9cc.tdf ; ;
; db/cntr_gui.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cntr_gui.tdf ; ;
; db/cmpr_5cc.tdf ; yes ; Auto-Generated Megafunction ; D:/Electronics/MPU401 Core DE1/db/cmpr_5cc.tdf ; ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd ; ;
; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ;
+----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------------+---------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+------------+
; Estimated Total logic elements ; 5,270 ;
; ; ;
; Total combinational functions ; 3442 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 2179 ;
; -- 3 input functions ; 701 ;
; -- <=2 input functions ; 562 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 3151 ;
; -- arithmetic mode ; 291 ;
; ; ;
; Total registers ; 2986 ;
; -- Dedicated logic registers ; 2986 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 283 ;
; Total memory bits ; 126976 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; CLK_DIV[2] ;
; Maximum fan-out ; 1395 ;
; Total fan-out ; 24427 ;
; Average fan-out ; 3.54 ;
+---------------------------------------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DE1_TOP ; 3442 (315) ; 2986 (96) ; 126976 ; 0 ; 0 ; 0 ; 283 ; 0 ; |DE1_TOP ; work ;
; |OSD:OSD_inst| ; 559 (559) ; 59 (59) ; 17408 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst ; work ;
; |char_ram:char_ram_inst| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|char_ram:char_ram_inst ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component ; work ;
; |altsyncram_vrr1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component|altsyncram_vrr1:auto_generated ; work ;
; |font_rom:font_rom_inst| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|font_rom:font_rom_inst ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component ; work ;
; |altsyncram_8681:auto_generated| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component|altsyncram_8681:auto_generated ; work ;
; |PLL:PLL_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|PLL:PLL_inst ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|PLL:PLL_inst|altpll:altpll_component ; work ;
; |SEG7_LUT_4:SEG7_LUT_4_inst| ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|SEG7_LUT_4:SEG7_LUT_4_inst ; work ;
; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|SEG7_LUT_4:SEG7_LUT_4_inst|SEG7_LUT:u0 ; work ;
; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|SEG7_LUT_4:SEG7_LUT_4_inst|SEG7_LUT:u1 ; work ;
; |SEG7_LUT:u2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|SEG7_LUT_4:SEG7_LUT_4_inst|SEG7_LUT:u2 ; work ;
; |SEG7_LUT:u3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|SEG7_LUT_4:SEG7_LUT_4_inst|SEG7_LUT:u3 ; work ;
; |async_receiver:async_receiver_inst| ; 40 (40) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|async_receiver:async_receiver_inst ; work ;
; |async_transmitter:async_transmitter_inst| ; 33 (33) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|async_transmitter:async_transmitter_inst ; work ;
; |cpu68:cpu68_inst| ; 1025 (1025) ; 171 (171) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|cpu68:cpu68_inst ; work ;
; |internal_ram:internal_ram_inst| ; 56 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst ; work ;
; |altsyncram:altsyncram_component| ; 56 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component ; work ;
; |altsyncram_8eg1:auto_generated| ; 56 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated ; work ;
; |altsyncram_bob2:altsyncram1| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|altsyncram_bob2:altsyncram1 ; work ;
; |sld_mod_ram_rom:mgl_prim2| ; 56 (35) ; 33 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2 ; work ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ; work ;
; |keyboard:keyboard_inst| ; 50 (50) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|keyboard:keyboard_inst ; work ;
; |ram:ram_inst| ; 62 (0) ; 37 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst ; work ;
; |altsyncram:altsyncram_component| ; 62 (0) ; 37 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component ; work ;
; |altsyncram_9dg1:auto_generated| ; 62 (0) ; 37 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated ; work ;
; |altsyncram_7ub2:altsyncram1| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1 ; work ;
; |sld_mod_ram_rom:mgl_prim2| ; 62 (40) ; 37 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2 ; work ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 22 (22) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ; work ;
; |rom:rom_inst| ; 64 (0) ; 38 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst ; work ;
; |altsyncram:altsyncram_component| ; 64 (0) ; 38 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component ; work ;
; |altsyncram_9ed1:auto_generated| ; 64 (0) ; 38 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated ; work ;
; |altsyncram_cpc2:altsyncram1| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|altsyncram_cpc2:altsyncram1 ; work ;
; |sld_mod_ram_rom:mgl_prim2| ; 64 (41) ; 38 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2 ; work ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 23 (23) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ; work ;
; |sld_hub:auto_hub| ; 230 (1) ; 148 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_hub:auto_hub ; work ;
; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 229 (183) ; 148 (119) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ;
; |sld_rom_sr:hub_info_reg| ; 29 (29) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ;
; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ;
; |sld_signaltap:auto_signaltap_0| ; 886 (1) ; 2214 (230) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0 ; work ;
; |sld_signaltap_impl:sld_signaltap_body| ; 885 (0) ; 1984 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; work ;
; |sld_signaltap_implb:sld_signaltap_body| ; 885 (19) ; 1984 (490) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body ; work ;
; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 21 (0) ; 58 (58) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; work ;
; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; work ;
; |decode_rqf:auto_generated| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated ; work ;
; |lpm_mux:mux| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; work ;
; |mux_eoc:auto_generated| ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_eoc:auto_generated ; work ;
; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ;
; |altsyncram_ne54:auto_generated| ; 0 (0) ; 0 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated ; work ;
; |lpm_shiftreg:segment_offset_config_deserialize| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; work ;
; |lpm_shiftreg:status_register| ; 18 (18) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register ; work ;
; |sld_buffer_manager:sld_buffer_manager_inst| ; 77 (77) ; 54 (54) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; work ;
; |sld_ela_control:ela_control| ; 539 (2) ; 1170 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control ; work ;
; |lpm_shiftreg:\storage_on_enable_bit:trigger_condition_deserialize| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:\storage_on_enable_bit:trigger_condition_deserialize ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 230 (0) ; 575 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 345 (345) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 230 (0) ; 230 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; work ;
; |sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic| ; 268 (0) ; 575 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic ; work ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 345 (345) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|lpm_shiftreg:trigger_condition_deserialize ; work ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 268 (38) ; 230 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\storage_combinational:combinational_qualifier_basic:combinational_qualifier_basic|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; work ;
; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 39 (39) ; 11 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_gap_detector:\stp_non_zero_ram_gen:gap_detect_on:gap_detector| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_gap_detector:\stp_non_zero_ram_gen:gap_detect_on:gap_detector ; work ;
; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 193 (11) ; 176 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; work ;
; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 9 (0) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; work ;
; |cntr_mdi:auto_generated| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_mdi:auto_generated ; work ;
; |lpm_counter:read_pointer_counter| ; 9 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; work ;
; |cntr_v1j:auto_generated| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_v1j:auto_generated ; work ;
; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; work ;
; |cntr_1ci:auto_generated| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_1ci:auto_generated ; work ;
; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; work ;
; |cntr_gui:auto_generated| ; 3 (3) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_gui:auto_generated ; work ;
; |lpm_shiftreg:info_data_shift_out| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; work ;
; |lpm_shiftreg:ram_data_shift_out| ; 116 (116) ; 116 (116) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; work ;
; |lpm_shiftreg:status_data_shift_out| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; work ;
; |sld_rom_sr:crc_rom_sr| ; 17 (17) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; work ;
; |top_sync_vg_pattern:top_sync_vg_pattern_inst| ; 94 (2) ; 79 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|top_sync_vg_pattern:top_sync_vg_pattern_inst ; work ;
; |pattern_vg:pattern_vg| ; 12 (12) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|top_sync_vg_pattern:top_sync_vg_pattern_inst|pattern_vg:pattern_vg ; work ;
; |sync_vg:sync_vg| ; 80 (80) ; 51 (51) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_TOP|top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg ; work ;
+---------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+
; OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component|altsyncram_vrr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; None ;
; OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component|altsyncram_8681:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 2048 ; 8 ; -- ; -- ; 16384 ; fontRomData.mif ;
; internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|altsyncram_bob2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 128 ; 8 ; 128 ; 8 ; 1024 ; None ;
; ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; None ;
; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|altsyncram_cpc2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 6801v0b55p.mif ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 116 ; 512 ; 116 ; 59392 ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------+-----------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------+-----------------------------------------------+
; Altera ; RAM: 2-PORT ; 13.0 ; N/A ; N/A ; |DE1_TOP|OSD:OSD_inst|char_ram:char_ram_inst ; D:/Electronics/MPU401 Core DE1/char_ram.v ;
; Altera ; ROM: 1-PORT ; N/A ; N/A ; N/A ; |DE1_TOP|OSD:OSD_inst|font_rom:font_rom_inst ; D:/Electronics/MPU401 Core DE1/font_rom.v ;
; Altera ; ALTPLL ; 13.0 ; N/A ; N/A ; |DE1_TOP|PLL:PLL_inst ; D:/Electronics/MPU401 Core DE1/PLL.v ;
; Altera ; RAM: 1-PORT ; 13.0 ; N/A ; N/A ; |DE1_TOP|internal_ram:internal_ram_inst ; D:/Electronics/MPU401 Core DE1/internal_ram.v ;
; Altera ; RAM: 1-PORT ; 13.0 ; N/A ; N/A ; |DE1_TOP|ram:ram_inst ; D:/Electronics/MPU401 Core DE1/ram.v ;
; Altera ; ROM: 1-PORT ; 13.0 ; N/A ; N/A ; |DE1_TOP|rom:rom_inst ; D:/Electronics/MPU401 Core DE1/rom.v ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------+-----------------------------------------------+
Encoding Type: One-Hot
+-------------------------------------------------------+
; State Machine - |DE1_TOP|keyboard:keyboard_inst|state ;
+---------------+---------------------------------------+
; Name ; state.receive ;
+---------------+---------------------------------------+
; state.idle ; 0 ;
; state.receive ; 1 ;
+---------------+---------------------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE1_TOP|cpu68:cpu68_inst|state ;
+-------------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+------------------+------------------+------------------+------------------+---------------------+---------------------+---------------------+---------------------+----------------------+----------------------+--------------------+-----------------+----------------------+---------------------+----------------------+----------------------+--------------------+---------------------+---------------------+---------------------+---------------------+--------------------+--------------------+------------------+-----------------+--------------------+------------------+-----------------+-----------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+-------------------+-----------------+-------------------+------------------+---------------------+---------------------+--------------------+-------------------------+--------------------+-------------------+---------------------+----------------------+--------------------+-------------------+-------------------+
; Name ; state.vect_hi_state ; state.vect_lo_state ; state.pshx_hi_state ; state.pshx_lo_state ; state.pulx_hi_state ; state.pulx_lo_state ; state.pshb_state ; state.pulb_state ; state.psha_state ; state.pula_state ; state.rti_pch_state ; state.rti_pcl_state ; state.rti_ixh_state ; state.rti_ixl_state ; state.rti_accb_state ; state.rti_acca_state ; state.rti_cc_state ; state.rti_state ; state.int_mask_state ; state.int_wai_state ; state.int_accb_state ; state.int_acca_state ; state.int_cc_state ; state.int_ixh_state ; state.int_ixl_state ; state.int_pch_state ; state.int_pcl_state ; state.rts_lo_state ; state.rts_hi_state ; state.bsr1_state ; state.bsr_state ; state.branch_state ; state.jsr1_state ; state.jsr_state ; state.jmp_state ; state.mul7_state ; state.mul6_state ; state.mul5_state ; state.mul4_state ; state.mul3_state ; state.mul2_state ; state.mul1_state ; state.mul0_state ; state.muld_state ; state.mulea_state ; state.mul_state ; state.error_state ; state.halt_state ; state.execute_state ; state.write16_state ; state.write8_state ; state.immediate16_state ; state.read16_state ; state.read8_state ; state.indexed_state ; state.extended_state ; state.decode_state ; state.fetch_state ; state.reset_state ;
+-------------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+------------------+------------------+------------------+------------------+---------------------+---------------------+---------------------+---------------------+----------------------+----------------------+--------------------+-----------------+----------------------+---------------------+----------------------+----------------------+--------------------+---------------------+---------------------+---------------------+---------------------+--------------------+--------------------+------------------+-----------------+--------------------+------------------+-----------------+-----------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+-------------------+-----------------+-------------------+------------------+---------------------+---------------------+--------------------+-------------------------+--------------------+-------------------+---------------------+----------------------+--------------------+-------------------+-------------------+
; state.reset_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.fetch_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.decode_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.extended_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.indexed_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; state.read8_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.read16_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.immediate16_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.write8_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.write16_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.execute_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.halt_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.error_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mulea_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.muld_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul0_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul1_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul2_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul3_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul4_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul5_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul6_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.mul7_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.jmp_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.jsr_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.jsr1_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.branch_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.bsr_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.bsr1_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rts_hi_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rts_lo_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_pcl_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_pch_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_ixl_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_ixh_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_cc_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_acca_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_accb_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_wai_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.int_mask_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_cc_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_acca_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_accb_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_ixl_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_ixh_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_pcl_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.rti_pch_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pula_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.psha_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pulb_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pshb_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pulx_lo_state ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pulx_hi_state ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pshx_lo_state ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.pshx_hi_state ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.vect_lo_state ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.vect_hi_state ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+------------------+------------------+------------------+------------------+---------------------+---------------------+---------------------+---------------------+----------------------+----------------------+--------------------+-----------------+----------------------+---------------------+----------------------+----------------------+--------------------+---------------------+---------------------+---------------------+---------------------+--------------------+--------------------+------------------+-----------------+--------------------+------------------+-----------------+-----------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+-------------------+-----------------+-------------------+------------------+---------------------+---------------------+--------------------+-------------------------+--------------------+-------------------+---------------------+----------------------+--------------------+-------------------+-------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis ;
+---------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+---------------+------------------------------------------------------------------+--------------------------------------------+
; ICC_INT ; yes ; yes ;
; SCI_INT ; yes ; yes ;
; TMR_INT ; yes ; yes ;
; OCC_INT ; yes ; yes ;
+---------------+------------------------------------------------------------------+--------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; top_sync_vg_pattern:top_sync_vg_pattern_inst|pattern_vg:pattern_vg|ramp_values[0..19] ; Lost fanout ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|field ; Lost fanout ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|hv_offset[0..11] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_sync[0] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_sync[1] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_sync[2] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_sync[3..11] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_bp[0,1] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_bp[2] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_bp[3] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_bp[4] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_bp[5..11] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_fp[0] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_fp[1] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_fp[2] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_fp[3..11] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[0] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[1..3] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[4] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[5..7] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[8] ; Stuck at GND due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[9] ; Stuck at VCC due to stuck port data_in ;
; top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_total[10,11] ; Stuck at GND due to stuck port data_in ;
; cpu68:cpu68_inst|nmi_req ; Stuck at GND due to stuck port data_in ;
; cpu68:cpu68_inst|nmi_ack ; Stuck at GND due to stuck port data_in ;
; cpu68:cpu68_inst|state.halt_state ; Lost fanout ;
; keyboard:keyboard_inst|state~5 ; Lost fanout ;
; cpu68:cpu68_inst|state.error_state ; Stuck at GND due to stuck port data_in ;
; CLK_DIV[3] ; Lost fanout ;
; OSD:OSD_inst|char_pixel[9,10] ; Lost fanout ;
; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ; Stuck at GND due to stuck port data_in ;
; internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ; Stuck at GND due to stuck port data_in ;
; ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 92 ; ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+-----------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+--------------------------+---------------------------+----------------------------------------+
; cpu68:cpu68_inst|nmi_req ; Stuck at GND ; cpu68:cpu68_inst|nmi_ack ;
; ; due to stuck port data_in ; ;
+--------------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 2986 ;
; Number of registers using Synchronous Clear ; 76 ;
; Number of registers using Synchronous Load ; 85 ;
; Number of registers using Asynchronous Clear ; 1160 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1364 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; OSD:OSD_inst|BREAKPOINT[30] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[31] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[28] ; 4 ;
; OSD:OSD_inst|BREAKPOINT[11] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[10] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[9] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[6] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[5] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[7] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[0] ; 4 ;
; OSD:OSD_inst|BREAKPOINT[3] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[2] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[1] ; 5 ;
; OSD:OSD_inst|BREAKPOINT[18] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[19] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[16] ; 4 ;
; OSD:OSD_inst|BREAKPOINT[13] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[15] ; 7 ;
; OSD:OSD_inst|BREAKPOINT[12] ; 4 ;
; OSD:OSD_inst|BREAKPOINT[27] ; 7 ;
; OSD:OSD_inst|BREAKPOINT[26] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[25] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[23] ; 6 ;
; OSD:OSD_inst|BREAKPOINT[21] ; 6 ;
; keyboard:keyboard_inst|rxregister[1] ; 3 ;
; keyboard:keyboard_inst|rxregister[0] ; 3 ;
; keyboard:keyboard_inst|rxregister[7] ; 3 ;
; keyboard:keyboard_inst|rxregister[4] ; 3 ;
; keyboard:keyboard_inst|rxregister[6] ; 3 ;
; keyboard:keyboard_inst|rxregister[5] ; 3 ;
; keyboard:keyboard_inst|rxregister[3] ; 3 ;
; keyboard:keyboard_inst|rxregister[2] ; 3 ;
; keyboard:keyboard_inst|rxregister[8] ; 3 ;
; keyboard:keyboard_inst|clksr[1] ; 2 ;
; keyboard:keyboard_inst|clksr[0] ; 2 ;
; keyboard:keyboard_inst|datasr[1] ; 2 ;
; keyboard:keyboard_inst|rxregister[9] ; 1 ;
; keyboard:keyboard_inst|datasr[0] ; 1 ;
; keyboard:keyboard_inst|rxregister[10] ; 1 ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; 1 ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_out_mode_ff ; 2 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] ; 1 ;
; Total number of inverted registers = 52 ; ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |DE1_TOP|keyboard:keyboard_inst|rxtimeout[4] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ;
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |DE1_TOP|async_receiver:async_receiver_inst|bit_spacing[0] ;
; 3:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ;
; 3:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ;
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] ;
; 3:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |DE1_TOP|top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|h_count[2] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_TOP|CTR_REG[2] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_TOP|CTR_REG[15] ;
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |DE1_TOP|async_receiver:async_receiver_inst|RxD_cnt_inv[1] ;
; 4:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |DE1_TOP|top_sync_vg_pattern:top_sync_vg_pattern_inst|sync_vg:sync_vg|v_count[8] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|accb[1] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|xreg[1] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|xreg[8] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[3] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[1] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[1] ;
; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |DE1_TOP|OSD:OSD_inst|BP_NIBBLE[2] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|acca[6] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|md[11] ;
; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |DE1_TOP|cpu68:cpu68_inst|md[7] ;
; 12:1 ; 12 bits ; 96 LEs ; 96 LEs ; 0 LEs ; Yes ; |DE1_TOP|OSD:OSD_inst|vid_out[7] ;
; 24:1 ; 4 bits ; 64 LEs ; 48 LEs ; 16 LEs ; Yes ; |DE1_TOP|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_9ed1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 24:1 ; 4 bits ; 64 LEs ; 48 LEs ; 16 LEs ; Yes ; |DE1_TOP|internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[2] ;
; 24:1 ; 4 bits ; 64 LEs ; 48 LEs ; 16 LEs ; Yes ; |DE1_TOP|ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[1] ;
; 3:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |DE1_TOP|keyboard:keyboard_inst|rxregister[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|state ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|alu_ctrl.alu_adc ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|alu_ctrl.alu_lsr16 ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |DE1_TOP|CHAR_WR_ADDR[1] ;
; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|state ;
; 4:1 ; 13 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector12 ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector45 ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector25 ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector40 ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |DE1_TOP|keyboard:keyboard_inst|state ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector14 ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector147 ;
; 5:1 ; 8 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector149 ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector54 ;
; 9:1 ; 8 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector20 ;
; 13:1 ; 6 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector177 ;
; 13:1 ; 8 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |DE1_TOP|cpu68:cpu68_inst|Selector168 ;
; 26:1 ; 8 bits ; 136 LEs ; 128 LEs ; 8 LEs ; No ; |DE1_TOP|comb ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ;
; 6:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][6] ;
; 6:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ;
; 6:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[3][6] ;
; 6:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[4][1] ;
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][6] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[3][1] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[4][0] ;
; 34:1 ; 4 bits ; 88 LEs ; 56 LEs ; 32 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ;
; 12:1 ; 8 bits ; 64 LEs ; 24 LEs ; 40 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ;
; 44:1 ; 4 bits ; 116 LEs ; 56 LEs ; 60 LEs ; Yes ; |DE1_TOP|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
; Source assignments for Top-level Entity: |DE1_TOP ;
+------------------------------+-------+------+-----------------+
; Assignment ; Value ; From ; To ;
+------------------------------+-------+------+-----------------+
; PRESERVE_REGISTER ; on ; - ; SCI_INT ;
; PRESERVE_REGISTER ; on ; - ; ICC_INT ;
; PRESERVE_REGISTER ; on ; - ; TMR_INT ;
; PRESERVE_REGISTER ; on ; - ; OCC_INT ;
; IGNORE_LCELL_BUFFERS ; off ; - ; IO_CS ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; IO_CS ;
; IGNORE_LCELL_BUFFERS ; off ; - ; INT_RAM_CS ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; INT_RAM_CS ;
; IGNORE_LCELL_BUFFERS ; off ; - ; RAM_CS ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; RAM_CS ;
; IGNORE_LCELL_BUFFERS ; off ; - ; ROM_CS ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; ROM_CS ;
; IGNORE_LCELL_BUFFERS ; off ; - ; CPU_DATA_IN[7] ;