async_receiver_inst.v

_// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
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// to the terms and conditions of the Altera Program License 
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// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sun Jun 17 06:58:56 2018

async_receiver async_receiver_inst
(
	.clk(clk) ,	// input  clk
	.RxD(RxD) ,	// input  RxD
	.RxD_data_ready(RxD_data_ready) ,	// output  RxD_data_ready
	.RxD_data(RxD_data) ,	// output [7:0] RxD_data
	.RxD_endofpacket(RxD_endofpacket) ,	// output  RxD_endofpacket
	.RxD_idle(RxD_idle) 	// output  RxD_idle
);

defparam async_receiver_inst.ClkFrequency = 74250000;
defparam async_receiver_inst.Baud = 9600;
//defparam async_receiver_inst.Baud8 = ;
defparam async_receiver_inst.Baud8GeneratorAccWidth = 16;