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async_receiver_inst.v.bak
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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sun Jun 17 06:58:56 2018
async_receiver async_receiver_inst
(
.clk(clk_sig) , // input clk_sig
.RxD(RxD_sig) , // input RxD_sig
.RxD_data_ready(RxD_data_ready_sig) , // output RxD_data_ready_sig
.RxD_data(RxD_data_sig) , // output [7:0] RxD_data_sig
.RxD_endofpacket(RxD_endofpacket_sig) , // output RxD_endofpacket_sig
.RxD_idle(RxD_idle_sig) // output RxD_idle_sig
);
defparam async_receiver_inst.ClkFrequency = 74250000;
defparam async_receiver_inst.Baud = 9600;
//defparam async_receiver_inst.Baud8 = ;
defparam async_receiver_inst.Baud8GeneratorAccWidth = 16;