cpu68_inst.v.bak

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
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// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat Jun 16 19:37:06 2018

cpu68 cpu68_inst
(
	.clk(clk_sig) ,	// input  clk_sig
	.rst(rst_sig) ,	// input  rst_sig
	.rw(rw_sig) ,	// output  rw_sig
	.vma(vma_sig) ,	// output  vma_sig
	.address(address_sig) ,	// output [15:0] address_sig
	.data_in(data_in_sig) ,	// input [7:0] data_in_sig
	.data_out(data_out_sig) ,	// output [7:0] data_out_sig
	.hold(hold_sig) ,	// input  hold_sig
	.halt(halt_sig) ,	// input  halt_sig
	.irq(irq_sig) ,	// input  irq_sig
	.nmi(nmi_sig) 	// input  nmi_sig
);