[Feature-request/CPU-ID] For x86 CPUs, provide a way to include the processor instruction set capabilities within the platform predicate component

[pavly-gerges]

Problem definition:

A request to build an API that adds the CPU-ID output values to the PlatformPredicate for x86 processors through the NativeVariant propositions.

Solutions:

1. Examine the Electrostatic-Sandbox SDK capabilities and downsides (e.g., mainly ONLY GNU/Linux systems).
2. Examine the OSHI JNA library and its downsides.
3. Examine the capability and the downsides of building a system call sub-library.

See:

• CentralProcessor.

[pavly-gerges]

A good example to start with, might be examining the output of this:
https://github.com/oshi/oshi/blob/master/oshi-demo/src/main/java/oshi/demo/ComputerID.java

[stephengold]

Another library that might be useful:

https://github.com/aecsocket/cpu-features-java

[pavly-gerges]

1. Examine the Electrostatic-Sandbox SDK capabilities and downsides (e.g., mainly ONLY GNU/Linux systems).

There is another interesting approach which is to introduce an API on the Electrostatic SDK, and link it with the Java binding Electrostatic4j....

The idea is to use the inline assembly which is the same on all platforms:

#include <stdio.h>

void cpuid(int level, int *eax, int *ebx, int *ecx, int *edx) {
    __asm__ __volatile__(
        "cpuid"
        : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
        : "a" (level)
    );
}

int main() {
    int eax, ebx, ecx, edx;

    // Query vendor string and highest CPUID function
    cpuid(0, &eax, &ebx, &ecx, &edx);

    char vendor[13];
    *(int*)&vendor[0] = ebx;  // Copy EBX
    *(int*)&vendor[4] = edx;  // Copy EDX
    *(int*)&vendor[8] = ecx;  // Copy ECX
    vendor[12] = '\0'; 
}

I would prefer this approach to better control the output... And, about building it can be provided in the form of simple native libraries for Mac, Windows, and Linux X86 platforms via GitHub CI/CD which is already up and running on the Electrostatic framework repository. What do you think? Are there any odds that might block us so far?

The complexity of loading this software component would be handled by JSnapLoader internally, so all you have to do is just add the additional dependency of the library that will be only responsible for this feature.

[stephengold]

That should be okay.

[pavly-gerges]

To better understand what are trying to do here, I grabbed the IA-32 Systems Programming Guide, and I guess this might be a close documentation to the specific operation we want, isn't it?

[stephengold]

I've given up trying to support IA-32. Going forward, my focus will be on 64-bit operating systems and CPUs. However, the bits that indicate instruction-set extensions on x86_64 CPUs are a superset of those on IA-32, so yes, this documentation is relevant.

There are many extension bits in x86_64 CPUID. The bits I care about are:

1. FMA (bit 12 in the ECX register after a CPUID with EAX=1)
2. SSE4.1 (bit 19 in ECX after a CPUID with EAX=1)
3. SSE4.2 (bit 20 in ECX after a CPUID with EAX=1)
4. AVX (bit 28 in ECX after a CPUID with EAX=1)
5. F16C (bit 29 in ECX after a CPUID with EAX=1)
6. AVX2 (bit 5 in the EBX register after a CPUID with EAX=7)
7. LZCNT (bit 5 in the ECX register after a CPUID with EAX=80000001h)
8. AVX512 (multiple bits)

Regarding AVX512, I need to ask Jorrit which CPUID bits are relevant to Jolt Physics.

I hope to run some measurements this weekend to estimate the performance impact of these extensions.

[stephengold]

Unfortunately, my laptop doesn't support AVX512. However, it does support the other 7 extensions.

With those 7 extensions turned on, I've seen throughput increases of 19.6% to 27.1% relative to baseline natives.

[stephengold]

Is there a plan to address this feature request?

[pavly-gerges]

Yeah, I am working on it. The plan is to first try to understand some x86 assembler keywords, so I would be able to address the issue from its complete perspective. Until then, if you are on a hurry, we can formulate an abstraction for any ready-to-use API to boot up the process; then I will take my time to do it from cores on other releases.

EDIT:
You seem to be understanding the issue more than I do, hence if you want to take it over, you are very welcome, and I could guide where to start.

[stephengold]

I'm willing to submit a PR. I would certainly appreciate any guidance you might offer.