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ElektraglideElektraglide
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Merge branch 'master' into adding-fpu
2 parents 01da690 + 56e55ea commit dbb241f

27 files changed

Lines changed: 934 additions & 264 deletions

‎hash/saitek_schess.xml‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ license:CC0-1.0
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</part>
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</software>
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21-
<software name="csss">
21+
<software name="classic">
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<description>Classical Style Super Strong</description>
2323
<year>1982</year>
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<publisher>SciSys</publisher>
@@ -29,4 +29,15 @@ license:CC0-1.0
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</part>
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</software>
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<software name="hyper">
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<description>Hyper Modern Super Strong</description>
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<year>1982</year>
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<publisher>SciSys</publisher>
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<part name="cart" interface="schess_cart">
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<dataarea name="rom" size="0x1000">
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<rom name="y02_mc" size="0x1000" crc="ee761d96" sha1="9c85398ae5ceec72c1a648baf39d1aa7bc315163" />
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</dataarea>
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</part>
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</software>
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</softwarelist>

‎scripts/src/cpu.lua‎

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Original file line numberDiff line numberDiff line change
@@ -4248,6 +4248,10 @@ if CPUS["C33"] then
42484248
MAME_DIR .. "src/devices/cpu/c33/c33helpers.ipp",
42494249
MAME_DIR .. "src/devices/cpu/c33/c33std.cpp",
42504250
MAME_DIR .. "src/devices/cpu/c33/c33std.h",
4251+
MAME_DIR .. "src/devices/cpu/c33/s1c33l17.cpp",
4252+
MAME_DIR .. "src/devices/cpu/c33/s1c33l17.h",
4253+
MAME_DIR .. "src/devices/cpu/c33/s1c33l27.cpp",
4254+
MAME_DIR .. "src/devices/cpu/c33/s1c33l27.h",
42514255
MAME_DIR .. "src/devices/cpu/c33/s1c33209.cpp",
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MAME_DIR .. "src/devices/cpu/c33/s1c33209.h",
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}

‎src/devices/cpu/c33/s1c33l17.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
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// license:BSD-3-Clause
2+
// copyright-holders:AJR
3+
4+
#include "emu.h"
5+
#include "s1c33l17.h"
6+
7+
// device type definitions
8+
DEFINE_DEVICE_TYPE(S1C33L17, s1c33l17_device, "s1c33l17", "Epson S1C33L17")
9+
DEFINE_DEVICE_TYPE(S1C33E07, s1c33e07_device, "s1c33e07", "Epson S1C33E07")
10+
11+
// FIXME: based on C33 PE Core, not STD Core
12+
s1c33l17_device::s1c33l17_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map)
13+
: c33std_cpu_device_base(mconfig, type, tag, owner, clock, map)
14+
{
15+
}
16+
17+
s1c33l17_device::s1c33l17_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
18+
: s1c33l17_device(mconfig, S1C33L17, tag, owner, clock, address_map_constructor(FUNC(s1c33l17_device::internal_map), this))
19+
{
20+
}
21+
22+
s1c33e07_device::s1c33e07_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
23+
: s1c33l17_device(mconfig, S1C33E07, tag, owner, clock, address_map_constructor(FUNC(s1c33e07_device::internal_map), this))
24+
{
25+
}
26+
27+
void s1c33l17_device::device_reset()
28+
{
29+
c33std_cpu_device_base::device_reset();
30+
31+
// TODO: gate ROM depending on boot mode
32+
m_pc = m_data.read_dword(0x00c00000);
33+
}
34+
35+
void s1c33l17_device::base_internal_map(address_map &map)
36+
{
37+
map(0x00000000, 0x00004fff).ram();
38+
map(0x00084000, 0x000847ff).ram();
39+
// 0x00300010-0x00300020 Misc Register (1)
40+
// 0x00300380-0x003003d5 I/O Ports
41+
// 0x00300520-0x0030055e A/D Converter
42+
// 0x00300660-0x0030033c Watchdog Timer (WDT)
43+
// 0x00300900-0x0030099f USB Function Controller
44+
// 0x00300a00-0x00300aff USB DMA Area
45+
// 0x00300b00-0x00300b4f Serial Interface (EFSIO)
46+
// 0x00300c00-0x00300c25 Extended Ports
47+
// 0x00300c40-0x00300c4d Misc Register (2)
48+
// 0x00301100-0x00301105 Intelligent DMA
49+
// 0x00301120-0x0030119e High-Speed DMA
50+
// 0x00301500-0x00301510 SRAM Controller
51+
// 0x00301600-0x00301610 SDRAM Controller
52+
// 0x00301700-0x0030171c SPI
53+
// 0x00301900-0x00301928 Real Time Clock
54+
// 0x00301b00-0x00301b24 Clock Management Unit
55+
}
56+
57+
void s1c33l17_device::internal_map(address_map &map)
58+
{
59+
base_internal_map(map);
60+
// 0x00300260-0x003002af Interrupt Controller
61+
// 0x00300300-0x0030031b Card Interface and Reed Solomon CODEC
62+
// 0x00300780-0x003007ea 16-bit Timer (4 channels)
63+
// 0x00301a00-0x00301aac LCD Controller (LCDC)
64+
// 0x00301c00-0x00301c30 I²S Interface
65+
}
66+
67+
void s1c33e07_device::internal_map(address_map &map)
68+
{
69+
base_internal_map(map);
70+
// 0x00300260-0x003002af Interrupt Controller (more sources than S1C33L17)
71+
// 0x00300300-0x0030031b Card Interface with ECC
72+
// 0x00300780-0x003007ea 16-bit Timer (6 channels)
73+
// 0x00301800-0x0030181c Direction Control Serial Interface (DCSIO)
74+
// 0x00301a00-0x00301aac LCD Controller (LCDC) (no 16bpp mode)
75+
// 0x00301c00-0x00301c30 I²S Interface (different from S1C33L17)
76+
}

‎src/devices/cpu/c33/s1c33l17.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
// license:BSD-3-Clause
2+
// copyright-holders:AJR
3+
4+
#ifndef MAME_CPU_C33_S1C33L17_H
5+
#define MAME_CPU_C33_S1C33L17_H
6+
7+
#pragma once
8+
9+
#include "c33std.h"
10+
11+
class s1c33l17_device : public c33std_cpu_device_base
12+
{
13+
public:
14+
s1c33l17_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
15+
16+
protected:
17+
s1c33l17_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map);
18+
19+
// device_t implementation
20+
virtual void device_reset() override ATTR_COLD;
21+
22+
void base_internal_map(address_map &map);
23+
24+
private:
25+
void internal_map(address_map &map);
26+
};
27+
28+
class s1c33e07_device : public s1c33l17_device
29+
{
30+
public:
31+
s1c33e07_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
32+
33+
private:
34+
void internal_map(address_map &map);
35+
};
36+
37+
// device type declarations
38+
DECLARE_DEVICE_TYPE(S1C33L17, s1c33l17_device)
39+
DECLARE_DEVICE_TYPE(S1C33E07, s1c33e07_device)
40+
41+
#endif // MAME_CPU_C33_S1C33L17_H

‎src/devices/cpu/c33/s1c33l27.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
// license:BSD-3-Clause
2+
// copyright-holders:AJR
3+
4+
#include "emu.h"
5+
#include "s1c33l27.h"
6+
7+
// device type definition
8+
DEFINE_DEVICE_TYPE(S1C33L27, s1c33l27_device, "s1c33l27", "Epson S1C33L27")
9+
10+
// FIXME: based on C33 PE Core, not STD Core
11+
s1c33l27_device::s1c33l27_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
12+
: c33std_cpu_device_base(mconfig, S1C33L27, tag, owner, clock, address_map_constructor(FUNC(s1c33l27_device::internal_map), this))
13+
{
14+
}
15+
16+
void s1c33l27_device::device_reset()
17+
{
18+
c33std_cpu_device_base::device_reset();
19+
20+
// TODO: gate ROM depending on boot mode
21+
m_pc = m_data.read_dword(0x00c00000);
22+
}
23+
24+
void s1c33l27_device::internal_map(address_map &map)
25+
{
26+
map(0x00000000, 0x00004fff).ram();
27+
map(0x00008000, 0x0000ffff).ram();
28+
map(0x00084000, 0x000847ff).ram();
29+
// 0x00300000-0x003000ff Misc Registers (MISC)
30+
// 0x00300100-0x003001ff Clock Management Unit (CMU)
31+
// 0x00300200-0x003002ff Interrupt Controller (ITC)
32+
// 0x00300300-0x003003ff I/O Ports (GPIO)
33+
// 0x00300400-0x003005ff Universal Serial Interface Ch.0, Ch.1 (USI)
34+
// 0x00300600-0x003006ff Universal Serial Interface with LCD Interface (USIL)
35+
// 0x00300700-0x003007ff Universal Serial Interface Ch.2 (USI)
36+
// 0x00300800-0x003008ff Port MUX (PMUX)
37+
// 0x00300900-0x003009ff Host Interface (HIF)
38+
// 0x00300a00-0x00300aff Real-time Clock (RTC)
39+
// 0x00300b00-0x00300bff BBRAM
40+
// 0x00300c00-0x00300dff USB Function Controller
41+
// 0x00300e00-0x00300e0f Prescaler (PSC)
42+
// 0x00300e10-0x00300eff UART
43+
// 0x00300f00-0x00300fff Card Interface (CARD)
44+
// 0x00301000-0x003010ff Watchdog Timer (WDT)
45+
// 0x00301100-0x0030115f Fine Mode 8-bit Timer Ch.0-Ch.5 (T8F)
46+
// 0x00301160-0x003011ff 16-bit PWM Timer Ch.0-Ch.3 (T16A6)
47+
// 0x00301200-0x003012ff 16-bit Audio PWM Timer Ch.0, Ch.1 (T16P)
48+
// 0x00301300-0x003013ff A/D Converter
49+
// 0x00301500-0x003015ff Remote Controller (REMC)
50+
// 0x00302000-0x003020ff LCD Controller
51+
// 0x00302100-0x003021ff DMA Controller (DMAC)
52+
// 0x00302200-0x0030221f SDRAM Controller (SDRAMC)
53+
// 0x00302220-0x003022ff SRAM Controller (SRAMC)
54+
// 0x00302300-0x003023ff Cache Controller
55+
// 0x00302400-0x003024ff I²S Bus Interface
56+
// 0x00302600-0x003026ff SD/MMC Interface (SD_MMC)
57+
}

‎src/devices/cpu/c33/s1c33l27.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
// license:BSD-3-Clause
2+
// copyright-holders:AJR
3+
4+
#ifndef MAME_CPU_C33_S1C33L27_H
5+
#define MAME_CPU_C33_S1C33L27_H
6+
7+
#pragma once
8+
9+
#include "c33std.h"
10+
11+
class s1c33l27_device : public c33std_cpu_device_base
12+
{
13+
public:
14+
s1c33l27_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
15+
16+
protected:
17+
// device_t implementation
18+
virtual void device_reset() override ATTR_COLD;
19+
20+
private:
21+
void internal_map(address_map &map);
22+
};
23+
24+
// device type declaration
25+
DECLARE_DEVICE_TYPE(S1C33L27, s1c33l27_device)
26+
27+
#endif // MAME_CPU_C33_S1C33L27_H

‎src/devices/cpu/powerpc/ppccom.cpp‎

Lines changed: 16 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// license:BSD-3-Clause
2-
// copyright-holders:Aaron Giles, R. Belmont©
2+
// copyright-holders:Aaron Giles, R. Belmont
33
/***************************************************************************
44
55
ppccom.c
@@ -18,6 +18,8 @@
1818

1919
#include "endianness.h"
2020

21+
#include <bit>
22+
2123

2224
/***************************************************************************
2325
DEBUGGING
@@ -32,10 +34,10 @@
3234
CONSTANTS
3335
***************************************************************************/
3436

35-
static constexpr uint64_t DOUBLE_SIGN = (0x8000000000000000U);
36-
static constexpr uint64_t DOUBLE_EXP = (0x7ff0000000000000U);
37-
static constexpr uint64_t DOUBLE_FRAC = (0x000fffffffffffffU);
38-
static constexpr uint64_t DOUBLE_ZERO = (0);
37+
static constexpr uint64_t DOUBLE_SIGN = 0x8000000000000000U;
38+
static constexpr uint64_t DOUBLE_EXP = 0x7ff0000000000000U;
39+
static constexpr uint64_t DOUBLE_FRAC = 0x000fffffffffffffU;
40+
static constexpr uint64_t DOUBLE_ZERO = 0;
3941

4042

4143

@@ -215,9 +217,12 @@ DEFINE_DEVICE_TYPE(PPC740, ppc740_device, "ppc740", "IBM PowerPC 740")
215217
DEFINE_DEVICE_TYPE(PPC750, ppc750_device, "ppc750", "IBM PowerPC 750")
216218

217219

218-
ppc_device::ppc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock,
219-
int address_bits, int data_bits, powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor,
220-
address_map_constructor internal_map, uint32_t reservation_size)
220+
ppc_device::ppc_device(
221+
const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock,
222+
int address_bits, int data_bits,
223+
powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor,
224+
address_map_constructor internal_map,
225+
uint32_t reservation_size)
221226
: cpu_device(mconfig, type, tag, owner, clock)
222227
, device_vtlb_interface(mconfig, *this, AS_PROGRAM)
223228
, m_program_config("program", ENDIANNESS_BIG, data_bits, address_bits, 0, internal_map)
@@ -238,9 +243,11 @@ ppc_device::ppc_device(const machine_config &mconfig, device_type type, const ch
238243
, m_drcuml(nullptr)
239244
, m_drcfe(nullptr)
240245
, m_drcoptions(0)
241-
, m_reservation_mask(0xffff'ffff - (reservation_size - 1))
246+
, m_reservation_mask(~uint32_t(reservation_size - 1))
242247
, m_dasm(powerpc_disassembler())
243248
{
249+
assert(std::has_single_bit(reservation_size));
250+
244251
m_program_config.m_logaddr_width = 32;
245252
m_program_config.m_page_shift = POWERPC_MIN_PAGE_SHIFT;
246253

‎src/devices/cpu/powerpc/ppcdrc.cpp‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -760,8 +760,9 @@ void ppc_device::static_generate_exception(uint8_t exception, int recover, const
760760
alloc_handle(m_drcuml.get(), &exception_handle, name);
761761
UML_HANDLE(block, *exception_handle); // handle name
762762

763-
// DSIs and alignment exceptions report the faulting data address in DAR (ISIs uses SRR0/SRR1 instead)
764-
if (exception == EXCEPTION_DSI || exception == EXCEPTION_ALIGN) {
763+
// DSIs and alignment exceptions report the faulting data address in DAR (ISIs uses SRR0/SRR1 instead)
764+
if (exception == EXCEPTION_DSI || exception == EXCEPTION_ALIGN)
765+
{
765766
UML_GETEXP(block, I0); // getexp i0
766767
UML_MOV(block, SPR32(SPROEA_DAR), I0); // mov [dar],i0
767768
}
@@ -923,7 +924,15 @@ void ppc_device::static_generate_exception(uint8_t exception, int recover, const
923924
static_generate_memory_accessor
924925
------------------------------------------------------------------*/
925926

926-
void ppc_device::static_generate_memory_accessor(int mode, int size, bool iswrite, bool ismasked, bool isreserve, const char *name, uml::code_handle *&handleptr, uml::code_handle *masked)
927+
void ppc_device::static_generate_memory_accessor(
928+
int mode,
929+
int size,
930+
bool iswrite,
931+
bool ismasked,
932+
bool isreserve,
933+
const char *name,
934+
uml::code_handle *&handleptr,
935+
uml::code_handle *masked)
927936
{
928937
/* on entry, address is in I0; data for writes is in I1; masks are in I2 */
929938
/* on exit, read result is in I0 */

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