https://github.com/Engr315/P8_Pipeline_Dot/blob/c8a1ef428bfc964ac653a00259293405920f092a/verilog/vtests/accel_dot/accel_dot_tb.sv#L188 Add a check to TIMIT to make sure output data is valid before passing. Students figured out they can write TLAST early to get fewer cycles.
P8_Pipeline_Dot/verilog/vtests/accel_dot/accel_dot_tb.sv
Line 188 in c8a1ef4
Add a check to TIMIT to make sure output data is valid before passing. Students figured out they can write TLAST early to get fewer cycles.