diff --git a/verilog/vtests/accel_dot/accel_dot_tb.sv b/verilog/vtests/accel_dot/accel_dot_tb.sv
index e345a7f..d5870fa 100644
--- a/verilog/vtests/accel_dot/accel_dot_tb.sv
+++ b/verilog/vtests/accel_dot/accel_dot_tb.sv
@@ -49,6 +49,8 @@ module accel_dot_tb();
     bit [31:0] fp_hex;
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
+    
+    reg COMPUTE_FIN;
  
     accel_dot DUT ( 
         .clk, 
@@ -155,6 +157,9 @@ module accel_dot_tb();
     endtask
 
     task compute();
+    
+        COMPUTE_FIN = 'h0;
+        
         $display("Sending Input Vector");                
         for (i = 0; i < 3; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -181,8 +186,11 @@ module accel_dot_tb();
             assert( (mismatch > -0.000001) && (mismatch < +0.000001) ) else
                 $fatal(1, "Bad Test Response %h (%f), Expected %h (%f) mismatch:%f", 
                     fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch); 
+                    
             
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
     
     task timeit (
@@ -190,6 +198,7 @@ module accel_dot_tb();
         );
         
         cycles = 0;
+
         while ( ! (
             (OUTPUT_AXIS_TREADY === 'h1) && 
             (OUTPUT_AXIS_TVALID === 'h1) && 
@@ -201,6 +210,10 @@ module accel_dot_tb();
             assert (cycles < 4410) else 
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
+        
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
                         
     endtask
        
diff --git a/verilog/vtests/accel_dot_20_10/accel_dot_20_10_tb.sv b/verilog/vtests/accel_dot_20_10/accel_dot_20_10_tb.sv
index 2995b27..052464d 100644
--- a/verilog/vtests/accel_dot_20_10/accel_dot_20_10_tb.sv
+++ b/verilog/vtests/accel_dot_20_10/accel_dot_20_10_tb.sv
@@ -146,6 +146,8 @@ module accel_dot_20_10_tb();
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
  
+    reg COMPUTE_FIN;
+
     accel_dot #(
         .ROWS(ROWS),
         .COLS(COLS)
@@ -263,6 +265,9 @@ module accel_dot_20_10_tb();
     endtask
 
     task compute();
+         
+        COMPUTE_FIN = 'h0;
+
         $display("Sending Input Vector");                
         for (i = 0; i < ROWS; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -294,6 +299,8 @@ module accel_dot_20_10_tb();
             repeat(2) @(negedge clk);
 
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
 
     task timeit (
@@ -313,6 +320,10 @@ module accel_dot_20_10_tb();
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
                         
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
+
     endtask
     
 
diff --git a/verilog/vtests/dot/dot_tb.sv b/verilog/vtests/dot/dot_tb.sv
index 2601bb6..bed2ad9 100644
--- a/verilog/vtests/dot/dot_tb.sv
+++ b/verilog/vtests/dot/dot_tb.sv
@@ -50,6 +50,8 @@ module dot_tb();
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
  
+    reg COMPUTE_FIN;
+
     dot DUT ( 
         .clk, 
         .rst, 
@@ -155,6 +157,9 @@ module dot_tb();
     endtask
 
     task compute();
+
+        COMPUTE_FIN = 'h0;
+
         $display("Sending Input Vector");                
         for (i = 0; i < 3; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -183,6 +188,8 @@ module dot_tb();
                     fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch); 
             
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
     
     task timeit (
@@ -202,6 +209,10 @@ module dot_tb();
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
                         
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
+
     endtask
        
 
diff --git a/verilog/vtests/dot_20_10/dot_20_10_tb.sv b/verilog/vtests/dot_20_10/dot_20_10_tb.sv
index 45b7ce6..a27bfb6 100644
--- a/verilog/vtests/dot_20_10/dot_20_10_tb.sv
+++ b/verilog/vtests/dot_20_10/dot_20_10_tb.sv
@@ -39,6 +39,8 @@ module dot_20_10_tb();
     bit [31:0] fp_hex;
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
+    
+    reg COMPUTE_FIN;
  
     axis_dot_20_10 DUT ( 
         .aclk(clk), 
@@ -152,6 +154,9 @@ module dot_20_10_tb();
     endtask
 
     task compute();
+    
+        COMPUTE_FIN = 'h0;
+        
         $display("Sending Input Vector");                
         for (i = 0; i < 20; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -179,6 +184,8 @@ module dot_20_10_tb();
                     fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), error); 
             
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
 
     task timeit (
@@ -197,7 +204,11 @@ module dot_20_10_tb();
             assert (cycles < 44100) else 
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
-                        
+        
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
+ 
     endtask
     
 
diff --git a/verilog/vtests/dot_40_20/dot_40_20_tb.sv b/verilog/vtests/dot_40_20/dot_40_20_tb.sv
index cc48d91..eda24d8 100644
--- a/verilog/vtests/dot_40_20/dot_40_20_tb.sv
+++ b/verilog/vtests/dot_40_20/dot_40_20_tb.sv
@@ -41,6 +41,8 @@ module dot_40_20_tb();
     bit [31:0] fp_hex;
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
+    
+    reg COMPUTE_FIN;
  
     axis_dot_40_20 DUT ( 
         .aclk(clk), 
@@ -163,6 +165,9 @@ module dot_40_20_tb();
     endtask
 
     task compute();
+    
+        COMPUTE_FIN = 'h0;
+        
         $display("Sending Input Vector");                
         for (i = 0; i < ROWS ; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -191,6 +196,8 @@ module dot_40_20_tb();
                     fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch); 
             
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
     
     task timeit (
@@ -209,7 +216,11 @@ module dot_40_20_tb();
             assert (cycles < 44100) else 
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
-                        
+        
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
+
     endtask
        
 
diff --git a/verilog/vtests/dot_80_40/dot_80_40_tb.sv b/verilog/vtests/dot_80_40/dot_80_40_tb.sv
index a6aff6d..265ccf9 100644
--- a/verilog/vtests/dot_80_40/dot_80_40_tb.sv
+++ b/verilog/vtests/dot_80_40/dot_80_40_tb.sv
@@ -41,6 +41,8 @@ module dot_80_40_tb();
     bit [31:0] fp_hex;
     //used to access the FP Solutions table
     bit [31:0] sol_hex;
+    
+    reg COMPUTE_FIN;
  
     axis_dot_80_40 DUT ( 
         .aclk(clk), 
@@ -181,6 +183,9 @@ module dot_80_40_tb();
     endtask
 
     task compute();
+        
+        COMPUTE_FIN = 'h0;
+    
         $display("Sending Input Vector");                
         for (i = 0; i < ROWS ; ++i) begin
             inputs_table_lookup(i, fp_hex);
@@ -209,6 +214,8 @@ module dot_80_40_tb();
                     fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch); 
             
         end
+        $display( "Compute done, finish timing" );
+        COMPUTE_FIN = 'h1;
     endtask
     
     task timeit (
@@ -227,7 +234,11 @@ module dot_80_40_tb();
             assert (cycles < 44100) else 
                 $fatal(1, "Running too long, check OUTPUT_AXIS?");
         end
-                        
+        
+        @(posedge clk);
+        assert(COMPUTE_FIN == 'h1) else
+            $fatal(1, "Timing done before correctness check");
+
     endtask