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[Mips] Rename MipsExprKind to Specifier
Follow the X86 renaming. > "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation. > "Relocation specifier" is clear, aligns with Arm and IBM’s usage, and fits the assembler's role seamlessly. In addition, rename MipsMCExpr::getKind, which confusingly shadows the base class getKind.
1 parent c8a9a41 commit aa4e6d8

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7 files changed

+46
-47
lines changed

7 files changed

+46
-47
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -6353,7 +6353,7 @@ MCRegister MipsAsmParser::getReg(int RC, int RegNo) {
63536353
// e.g. "%lo foo", "(%lo(foo))", "%lo(foo)+1".
63546354
const MCExpr *MipsAsmParser::parseRelocExpr() {
63556355
auto getOp = [](StringRef Op) {
6356-
return StringSwitch<MipsMCExpr::MipsExprKind>(Op)
6356+
return StringSwitch<MipsMCExpr::Specifier>(Op)
63576357
.Case("call16", MipsMCExpr::MEK_GOT_CALL)
63586358
.Case("call_hi", MipsMCExpr::MEK_CALL_HI16)
63596359
.Case("call_lo", MipsMCExpr::MEK_CALL_LO16)
@@ -6384,7 +6384,7 @@ const MCExpr *MipsAsmParser::parseRelocExpr() {
63846384
MCAsmParser &Parser = getParser();
63856385
StringRef Name;
63866386
const MCExpr *Res = nullptr;
6387-
SmallVector<MipsMCExpr::MipsExprKind, 0> Ops;
6387+
SmallVector<MipsMCExpr::Specifier, 0> Ops;
63886388
while (parseOptionalToken(AsmToken::Percent)) {
63896389
if (Parser.parseIdentifier(Name) ||
63906390
Parser.parseToken(AsmToken::LParen, "expected '('"))

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -584,7 +584,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
584584
const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
585585

586586
Mips::Fixups FixupKind = Mips::Fixups(0);
587-
switch (MipsExpr->getKind()) {
587+
switch (MipsExpr->getSpecifier()) {
588588
case MipsMCExpr::MEK_None:
589589
case MipsMCExpr::MEK_Special:
590590
llvm_unreachable("Unhandled fixup kind!");

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp

+14-13
Original file line numberDiff line numberDiff line change
@@ -24,20 +24,20 @@ using namespace llvm;
2424

2525
#define DEBUG_TYPE "mipsmcexpr"
2626

27-
const MipsMCExpr *MipsMCExpr::create(MipsMCExpr::MipsExprKind Kind,
27+
const MipsMCExpr *MipsMCExpr::create(MipsMCExpr::Specifier S,
2828
const MCExpr *Expr, MCContext &Ctx) {
29-
return new (Ctx) MipsMCExpr(Kind, Expr);
29+
return new (Ctx) MipsMCExpr(S, Expr);
3030
}
3131

32-
const MipsMCExpr *MipsMCExpr::createGpOff(MipsMCExpr::MipsExprKind Kind,
32+
const MipsMCExpr *MipsMCExpr::createGpOff(MipsMCExpr::Specifier S,
3333
const MCExpr *Expr, MCContext &Ctx) {
34-
return create(Kind, create(MEK_NEG, create(MEK_GPREL, Expr, Ctx), Ctx), Ctx);
34+
return create(S, create(MEK_NEG, create(MEK_GPREL, Expr, Ctx), Ctx), Ctx);
3535
}
3636

3737
void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
3838
int64_t AbsVal;
3939

40-
switch (Kind) {
40+
switch (specifier) {
4141
case MEK_None:
4242
case MEK_Special:
4343
llvm_unreachable("MEK_None and MEK_Special are invalid");
@@ -129,8 +129,9 @@ void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
129129
OS << ')';
130130
}
131131

132-
bool MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm)
133-
const { // Look for the %hi(%neg(%gp_rel(X))) and %lo(%neg(%gp_rel(X)))
132+
bool MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
133+
const MCAssembler *Asm) const {
134+
// Look for the %hi(%neg(%gp_rel(X))) and %lo(%neg(%gp_rel(X)))
134135
// special cases.
135136
if (isGpOff()) {
136137
const MCExpr *SubExpr =
@@ -146,21 +147,21 @@ bool MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm)
146147

147148
if (!getSubExpr()->evaluateAsRelocatable(Res, Asm))
148149
return false;
149-
Res =
150-
MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
150+
Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(),
151+
getSpecifier());
151152
return !Res.getSymB();
152153
}
153154

154155
void MipsMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
155156
Streamer.visitUsedExpr(*getSubExpr());
156157
}
157158

158-
bool MipsMCExpr::isGpOff(MipsExprKind &Kind) const {
159-
if (getKind() == MEK_HI || getKind() == MEK_LO) {
159+
bool MipsMCExpr::isGpOff(Specifier &S) const {
160+
if (getSpecifier() == MEK_HI || getSpecifier() == MEK_LO) {
160161
if (const MipsMCExpr *S1 = dyn_cast<const MipsMCExpr>(getSubExpr())) {
161162
if (const MipsMCExpr *S2 = dyn_cast<const MipsMCExpr>(S1->getSubExpr())) {
162-
if (S1->getKind() == MEK_NEG && S2->getKind() == MEK_GPREL) {
163-
Kind = getKind();
163+
if (S1->getSpecifier() == MEK_NEG && S2->getSpecifier() == MEK_GPREL) {
164+
S = getSpecifier();
164165
return true;
165166
}
166167
}

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h

+10-11
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ namespace llvm {
1616

1717
class MipsMCExpr : public MCTargetExpr {
1818
public:
19-
enum MipsExprKind {
19+
enum Specifier {
2020
MEK_None,
2121
MEK_CALL_HI16,
2222
MEK_CALL_LO16,
@@ -47,20 +47,19 @@ class MipsMCExpr : public MCTargetExpr {
4747
};
4848

4949
private:
50-
const MipsExprKind Kind;
50+
const Specifier specifier;
5151
const MCExpr *Expr;
5252

53-
explicit MipsMCExpr(MipsExprKind Kind, const MCExpr *Expr)
54-
: Kind(Kind), Expr(Expr) {}
53+
explicit MipsMCExpr(Specifier S, const MCExpr *Expr)
54+
: specifier(S), Expr(Expr) {}
5555

5656
public:
57-
static const MipsMCExpr *create(MipsExprKind Kind, const MCExpr *Expr,
57+
static const MipsMCExpr *create(Specifier S, const MCExpr *Expr,
5858
MCContext &Ctx);
59-
static const MipsMCExpr *createGpOff(MipsExprKind Kind, const MCExpr *Expr,
59+
static const MipsMCExpr *createGpOff(Specifier S, const MCExpr *Expr,
6060
MCContext &Ctx);
6161

62-
/// Get the kind of this expression.
63-
MipsExprKind getKind() const { return Kind; }
62+
Specifier getSpecifier() const { return specifier; }
6463

6564
/// Get the child of this expression.
6665
const MCExpr *getSubExpr() const { return Expr; }
@@ -78,10 +77,10 @@ class MipsMCExpr : public MCTargetExpr {
7877
return E->getKind() == MCExpr::Target;
7978
}
8079

81-
bool isGpOff(MipsExprKind &Kind) const;
80+
bool isGpOff(Specifier &S) const;
8281
bool isGpOff() const {
83-
MipsExprKind Kind;
84-
return isGpOff(Kind);
82+
Specifier S;
83+
return isGpOff(S);
8584
}
8685
};
8786

‎llvm/lib/Target/Mips/MipsAsmPrinter.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1245,7 +1245,7 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
12451245
// and value for debug thread local expression.
12461246
void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const {
12471247
if (auto *MipsExpr = dyn_cast<MipsMCExpr>(Value)) {
1248-
if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) {
1248+
if (MipsExpr && MipsExpr->getSpecifier() == MipsMCExpr::MEK_DTPREL) {
12491249
switch (Size) {
12501250
case 4:
12511251
getTargetStreamer().emitDTPRel32Value(MipsExpr->getSubExpr());

‎llvm/lib/Target/Mips/MipsMCInstLower.cpp

+17-18
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,7 @@ void MipsMCInstLower::Initialize(MCContext *C) {
3535
MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
3636
MachineOperandType MOTy,
3737
int64_t Offset) const {
38-
MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
39-
MipsMCExpr::MipsExprKind TargetKind = MipsMCExpr::MEK_None;
38+
MipsMCExpr::Specifier TargetKind = MipsMCExpr::MEK_None;
4039
bool IsGpOff = false;
4140
const MCSymbol *Symbol;
4241
SmallString<128> Name;
@@ -167,7 +166,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
167166
llvm_unreachable("<unknown operand type>");
168167
}
169168

170-
const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
169+
const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, *Ctx);
171170

172171
if (Offset) {
173172
// Note: Offset can also be negative
@@ -212,7 +211,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
212211

213212
MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
214213
MachineBasicBlock *BB2,
215-
MipsMCExpr::MipsExprKind Kind) const {
214+
MipsMCExpr::Specifier Kind) const {
216215
const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::create(BB1->getSymbol(), *Ctx);
217216
const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::create(BB2->getSymbol(), *Ctx);
218217
const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Sym1, Sym2, *Ctx);
@@ -227,20 +226,20 @@ lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
227226
// Lower register operand.
228227
OutMI.addOperand(LowerOperand(MI->getOperand(0)));
229228

230-
MipsMCExpr::MipsExprKind Kind;
229+
MipsMCExpr::Specifier Spec;
231230
unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
232231
switch (TargetFlags) {
233232
case MipsII::MO_HIGHEST:
234-
Kind = MipsMCExpr::MEK_HIGHEST;
233+
Spec = MipsMCExpr::MEK_HIGHEST;
235234
break;
236235
case MipsII::MO_HIGHER:
237-
Kind = MipsMCExpr::MEK_HIGHER;
236+
Spec = MipsMCExpr::MEK_HIGHER;
238237
break;
239238
case MipsII::MO_ABS_HI:
240-
Kind = MipsMCExpr::MEK_HI;
239+
Spec = MipsMCExpr::MEK_HI;
241240
break;
242241
case MipsII::MO_ABS_LO:
243-
Kind = MipsMCExpr::MEK_LO;
242+
Spec = MipsMCExpr::MEK_LO;
244243
break;
245244
default:
246245
report_fatal_error("Unexpected flags for lowerLongBranchLUi");
@@ -249,33 +248,33 @@ lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
249248
if (MI->getNumOperands() == 2) {
250249
const MCExpr *Expr =
251250
MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
252-
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
251+
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
253252
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
254253
} else if (MI->getNumOperands() == 3) {
255254
// Create %hi($tgt-$baltgt).
256255
OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
257-
MI->getOperand(2).getMBB(), Kind));
256+
MI->getOperand(2).getMBB(), Spec));
258257
}
259258
}
260259

261260
void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
262261
MCInst &OutMI, int Opcode) const {
263262
OutMI.setOpcode(Opcode);
264263

265-
MipsMCExpr::MipsExprKind Kind;
264+
MipsMCExpr::Specifier Spec;
266265
unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
267266
switch (TargetFlags) {
268267
case MipsII::MO_HIGHEST:
269-
Kind = MipsMCExpr::MEK_HIGHEST;
268+
Spec = MipsMCExpr::MEK_HIGHEST;
270269
break;
271270
case MipsII::MO_HIGHER:
272-
Kind = MipsMCExpr::MEK_HIGHER;
271+
Spec = MipsMCExpr::MEK_HIGHER;
273272
break;
274273
case MipsII::MO_ABS_HI:
275-
Kind = MipsMCExpr::MEK_HI;
274+
Spec = MipsMCExpr::MEK_HI;
276275
break;
277276
case MipsII::MO_ABS_LO:
278-
Kind = MipsMCExpr::MEK_LO;
277+
Spec = MipsMCExpr::MEK_LO;
279278
break;
280279
default:
281280
report_fatal_error("Unexpected flags for lowerLongBranchADDiu");
@@ -291,12 +290,12 @@ void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
291290
// Lower register operand.
292291
const MCExpr *Expr =
293292
MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
294-
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
293+
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
295294
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
296295
} else if (MI->getNumOperands() == 4) {
297296
// Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
298297
OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
299-
MI->getOperand(3).getMBB(), Kind));
298+
MI->getOperand(3).getMBB(), Spec));
300299
}
301300
}
302301

‎llvm/lib/Target/Mips/MipsMCInstLower.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
4141
MCOperand LowerSymbolOperand(const MachineOperand &MO,
4242
MachineOperandType MOTy, int64_t Offset) const;
4343
MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
44-
MipsMCExpr::MipsExprKind Kind) const;
44+
MipsMCExpr::Specifier Kind) const;
4545
void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
4646
void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
4747
int Opcode) const;

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